|
|
PDF SM-BF50 Data sheet ( Hoja de datos )
| Número de pieza | SM-BF50 | |
| Descripción | 50OHM DC to 2 GHz | |
| Fabricantes | Mini-Circuits | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SM-BF50 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
|
No Preview Available !
Standard EEPROM ICs
SLx 24C64
64 Kbit (8192 × 8 bit)
Serial CMOS-EEPROM with
I2C Synchronous 2-Wire Bus
Data Sheet Preliminary 1998-07-27
1 page  
SLx 24C64
Pin Definitions and Functions
Table 1
Pin No.
Symbol
1, 2, 3
CS0, CS1, CS2
4 VSS
5 SDA
6 SCL
7 WP
8 VCC
Function
Chip select inputs
Ground
Serial bidirectional data bus
Serial clock input
Write protection input
Supply voltage
Pin Description
Serial Clock (SCL)
The SCL input is used to clock data into the device on the rising edge and to clock data
out of the device on the falling edge.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses, data or control information into the
device or to transfer data out of the device. The output is open drain, performing a wired
AND function with any number of other open drain or open collector devices. The SDA
bus requires a pull-up resistor to VCC.
Chip Select (CS0, CS1, CS2)
The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven
to VCC or VSS. These inputs allow the selection of one of eight possible devices sharing
a common bus.
Write Protection (WP)
WP switched to VSS allows normal read/write operations.
WP switched to VCC protects the EEPROM against changes (hardware write protection).
Semiconductor Group
5 Preliminary 1998-07-27
5 Page 
SLx 24C64
5 Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one
programming procedure. Setting the Write Protection pin WP to VCC activates the
hardware write protection and therefore any programming is suppressed. For normal
operation WP has to be set to VSS.
5.1 Byte Write
Address Setting
Transmission of Data
Programming Cycle
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following two bytes AHI/ALO
with the EEPROM address (A0 to A12) are loaded into the
address counter of the EEPROM and acknowledged by the
EEPROM.
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the bytes AHI (A8 to A12)
and ALO (A0 to A7). The programming procedure consists of
an internally timed erase/write cycle. In the first step, the
selected byte is erased to “1”. With the next internal step, the
addressed byte is written according to the contents of the
buffer.
Bus Activity
Master
S
T
A Command Byte EEPROM Address EEPROM Address
R CSW
AHI
ALO
T
Data Byte
S
T
O
P
SDA Line S
0
P
Bus Activity
EEPROM
AAAA
CCCC
KKKK
IED02518
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3, Acknowledge Polling for further information.
Semiconductor Group
11 Preliminary 1998-07-27
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet SM-BF50.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SM-BF50 | 50OHM DC to 2 GHz | Mini-Circuits |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |