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부품번호 PA7540 기능
기능 PA7540 PEEL Array Programmable Electrically Erasable Logic Array
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PA7540 데이터시트, 핀배열, 회로
PA7540 PEEL Array™
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
General Description
The PA7540 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7540 is by far
the most powerful 24-pin PLD available today with 20 I/O
pins, 2 input/global-clocks and 40 registers/latches (20
buried logic cells and 20 I/O registers/latches). Its logic
array implements 84 sum-of-products logic functions. The
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely
flexible offering two output functions per cell (a total of 40
for all 20 logic cells). Logic cells are configurable as D, T,
and JK registers with independent or global clocks, resets,
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
presets, clock polarity, and other features, making the
PA7540 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. With pin
compatibility and super-set functionality to most 24-pin
PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
implement designs that exceed the architectures of such
devices. The PA7540 supports speeds as fast as
10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate
power consumption 80mA (55mA typical). Packaging
includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Anachip and popular third-party development tool
manufacturers provide development and programming
support for the PA7540.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
DIP
1
2
3
4
5
6
7
8
9
10
11
12
24
VCC
I/CLK1
23 I/O
22 I/O
I/O
I/O
I/O
21 I/O
I/O
20 I/O
19 I/O
I/O
I/O
I/O
18 I/O
I/O
17 I/O
16 I/O
I/O
I/O
GND
15 I/O
14 I/O
13 I/CLK2
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/CLK2
S O IC
4 3 2 1 28 27 26
I/O 5
25
I/O 6
24
I/O 7
23
NC 8
22
I/O 9
21
I/O 10
20
I/O 11
19
12 13 14 15 16 1718
P L C C -J
I/O I/O
I/O I/O
I/O I/O
NC NC
I/O I/O
I/O I/O
I/O I/O
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
P L C C -J N
08-14-001B
2 Input/
Global Clock Pins
I/C L K 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
G lobal C ells
I/O Cells
PA7540
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C L K 2
Logic Control C ells
G lo b al
C e lls
84 (42X2)
Array Inputs
true and
2 com plem ent
20
I/O
C e lls
(IO C )
20 I/O P ins
Logic
Array
20 Buried
logic
Logic
A
B
C o ntro l
C Cells
D (LCC)
20
Logic functions
to I/O cells
4 sum term s
4 product term s
for Global Cells
80 sum terms
(four per LCC)
20
20 Logic Control Cells
2 output functions per cell
(40 total output functions possible)
08-14-002A
1 04-02-051B




PA7540 pdf, 반도체, 판매, 대치품
Group A & B
Input with optional
register/latch
QD
I/O
A DQ
B
C
D
1
2
OE
I/O with
independent
output enable
08-14-008A
Figure 8. LCC & IOC With Two Outputs
CLK1
CLK2
PCLK
Reg-Type
Preset
Reset
MUX
MUX
Global Cell: LCC & IOC
Figure 9. Global Cells
Reg-Type from Global Cell
LCC Clocks
IOC Clocks
LCC Reg-Type
LCC Presets
LCC Resets
08-14-009A
Global Cells
The global cells, shown in Figure 9, are used to direct
global clock signals and/or control terms to the LCCs and
IOCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for IOC clocks
enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-of-
products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 10). The PA7540 provides two
global cells that divides the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful WinPLACE Development
Software (free to qualified PLD designers).
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
P
DQ
R
Register Type Change Feature
Global Cell can dynamically change user-
selected LCC registers from D to T or from D
to JK. This saves product terms for loadable
counters or state machines. Use as D register
to load, use as T or JK to count. Timing allows
dynamic operation.
P
TQ
R
Exam ple:
Product terms for 10 bit loadable binary counter
D uses 57 product terms (47 count, 10 load)
T uses 30 product terms (10 count, 20 load)
D/T uses 20 product terms (10 count, 10 load)
08-14-010A
Figure 10. Register Type Change Feature
internal signals to be simulated and analyzed via a
waveform display.(See Figures 10a-c)
PEEL™ Array development is also supported by popular
development tools, such as ABEL via Anachip’s PEEL™
Array fitters. A special smart translator utility adds the
capability to directly convert JEDEC files for other devices
into equivalent JEDEC files for pin-compatible PEEL™
Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE -
reprogrammability is also useful for production, allowing
unexpected changes to be made quickly and without
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PA7540 전자부품, 판매, 대치품
Table 4. A.C Electrical Characteristics Combinatorial
Over the Operating Range
Symbol
tPDI
tPDX
tIA
tAL
tLC
tLO
tOD, tOE
tOX
Parameter6,12
Propagation delay Internal (tAL + tLC)
Propagation delay External (tIA + tAL +tLC + tLO)
Input or I/O pin to array input
Array input to LCC
LCC input to LCC output10
LCC output to output pin
Output Disable, Enable from LCC output7
Output Disable, Enable from input pin7
-15/I-15
Min Max
10
15
2
9
1
3
3
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Figure 14. Combinatorial Timing - Waveforms and Block Diagram
7 04-02-051B

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