PA7540JNI-15 Datasheet PDF - ETC
| Part Number | PA7540JNI-15 | |
| Description | PA7540 PEEL Array Programmable Electrically Erasable Logic Array | |
| Manufacturers | ETC | |
| Logo |  |
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PA7540 PEEL Array™
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
General Description
The PA7540 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7540 is by far
the most powerful 24-pin PLD available today with 20 I/O
pins, 2 input/global-clocks and 40 registers/latches (20
buried logic cells and 20 I/O registers/latches). Its logic
array implements 84 sum-of-products logic functions. The
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely
flexible offering two output functions per cell (a total of 40
for all 20 logic cells). Logic cells are configurable as D, T,
and JK registers with independent or global clocks, resets,
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
presets, clock polarity, and other features, making the
PA7540 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. With pin
compatibility and super-set functionality to most 24-pin
PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
implement designs that exceed the architectures of such
devices. The PA7540 supports speeds as fast as
10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate
power consumption 80mA (55mA typical). Packaging
includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Anachip and popular third-party development tool
manufacturers provide development and programming
support for the PA7540.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
DIP
1
2
3
4
5
6
7
8
9
10
11
12
24
VCC
I/CLK1
23 I/O
22 I/O
I/O
I/O
I/O
21 I/O
I/O
20 I/O
19 I/O
I/O
I/O
I/O
18 I/O
I/O
17 I/O
16 I/O
I/O
I/O
GND
15 I/O
14 I/O
13 I/CLK2
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/CLK2
S O IC
4 3 2 1 28 27 26
I/O 5
25
I/O 6
24
I/O 7
23
NC 8
22
I/O 9
21
I/O 10
20
I/O 11
19
12 13 14 15 16 1718
P L C C -J
I/O I/O
I/O I/O
I/O I/O
NC NC
I/O I/O
I/O I/O
I/O I/O
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
P L C C -J N
08-14-001B
2 Input/
Global Clock Pins
I/C L K 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
G lobal C ells
I/O Cells
PA7540
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C L K 2
Logic Control C ells
G lo b al
C e lls
84 (42X2)
Array Inputs
true and
2 com plem ent
20
I/O
C e lls
(IO C )
20 I/O P ins
Logic
Array
20 Buried
logic
Logic
A
B
C o ntro l
C Cells
D (LCC)
20
Logic functions
to I/O cells
4 sum term s
4 product term s
for Global Cells
80 sum terms
(four per LCC)
20
20 Logic Control Cells
2 output functions per cell
(40 total output functions possible)
08-14-002A
1 04-02-051B
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waste. Programming of PEEL™ Arrays is supported by
many popular third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 12 - WinPLACE LCC and IOC screen
Figure 11 - WinPLACE Architectural Editor for
PA7540
Figure 13 - WinPLACE waveform and
simulator screen
5 04-02-051B
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| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ PA7540JNI-15.PDF Datasheet ] | |
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