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PDF RMPA0913C-58 Data sheet ( Hoja de datos )
| Número de pieza | RMPA0913C-58 | |
| Descripción | 3.5V AMPS/CDMA Power Amplifier | |
| Fabricantes | ETC | |
| Logotipo |  |
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RMPA0913C-58
3.5V AMPS/CDMA Power Amplifier
PRODUCT INFORMATION
Description
The RMPA0913C-58 is a monolithic high efficiency power amplifier for AMPS/CDMA dual mode applications in the
824 to 849 MHz frequency band. Performance parameters may be slightly adjusted by “tweaking” off-chip
matching components. The amplifier circuit design is a single ended configuration that utilizes harmonic tuning for
increased power added efficiency and linearity.The device uses Raytheon’s Pseudomorphic High Electron Mobility
Transistor (pHEMT) process.
Features
Positive supply voltage of 3.5V, nominal
Power Added Efficiency of 56%, typical, at power out of 31.5 dBm
Power Added Efficiency of 40%, typical, for CDMA power out of 28.5 dBm
Small outline metal based quad plastic package
Absolute
Maximum
Ratings
Parameter
Positive DC Voltage
Negative DC Voltage
Simultaneous (Vd-Vg)
RF Input Power (from 50-Ohm source)
Operating Case Temperature (Case)
Storage Temperature Range
Thermal Resistance
Symbol
Vd1,Vd2
Vg1,Vg2
Vdg
PIN
TC
TStg
RTj-c
Value
+9
-6
+12
+10
-30 to 110
-35 to 110
15
Units
Volts
Volts
Volts
dBm
°C
°C
°C/W
Electrical
Characteristics
(Specifications at
25 oC operating free
air temperature
unless otherwise
stated)
Parameter
Min Typ Max Unit
Frequency Range
824
Gain (Small Signal)
Gain Variation vs Temp
Gain Linearity
(0 dBm ≤ Pout ≤ 28.5 dBm) -1.5
Noise Power (869-894 MHz)
Input VSWR (50Ω)
Stability (All spurious) 1
Harmonics (Po ≤ 31.5 dBm)
Power Out
Vdd=3.5V, Pin=7 dBm
30
-0.02
32.5
849
+0.0
-140
2.0:1
-70
-35
MHz
dB
dB/°C
dB
dBm/Hz
---
dBc
dBc
dBm
Parameter
Efficiency
Pin = 7 dBm, Vdd= 3.5V
Po = 31.5 dBm, Vdd = 3.5V
Po = 28.5 dBm , Vdd= 3.5V
Po = 10 dBm , Vdd= 3.5V
ACPR 2 (Offset ≥ ± 900 kHz)
(Offset ≥ ± 1.98 MHz)
Noise Figure (over temp)
Vdd
Vg1, Vg2 (<4 mA)3
Case Operating Temp
Min Typ Max Unit
62
56
40
1.5
48
63
3.5
-1.75
-40
4.5
-0.25
+85
%
%
%
%
dBc
dBc
dB
Volts
Volts
°C
www.raytheon.com/micro
Notes:
1. Source/Load VSWR (All Angles) ≤ 3:1 In-Band, Load VSWR (All Angles) ≥ 20:1 Out of Band, Valid over Case Operating Temperature Range.
2. Po ≤ 28.5 dBm at Vdd=3.5V; CDMA Waveform measured using the ratio of the average power within a 1.23 MHz channel and within a 30
kHz bandwidth at the specified offset.
3. Vg1 adjusted for Idq (stage 1) = 35 mA, Vg2 adjusted for Idq (stage 2) = 155 mA.
Characteristic performance data and specifications are subject to change without notice.
Revised March 30, 2000
Page 1
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
1 page  
RMPA0913C-58
3.5V AMPS/CDMA Power Amplifier
Table 1
Further Important
Application
Information
Pin# Function
1 RF OUT AND VD2
2 RF OUT AND VD2
3 RF OUT AND VD2
4 G2 AC GND
5 GND
6 G1 AC GND
7 GND
8 RF IN
9 GND
10 VD1
11 VG2
12 VG1
13 PACKAGE BASE
AND GND
PRODUCT INFORMATION
Application hints
An optimal output match for dual mode applications is set by connecting capacitors C8 and
C9 to the package pin using approximately 0.233 inches of a 50 ohm transmission line.
These capacitors should be located adjacent to each other and separated by 0.010 inches.
Lower efficiency will result if a single capacitor of equivalent value were substituted. Fine
adjust the capacitors location to obtain a uniform saturated output power response versus
frequency using a single tone RF input. Saturated output power is typically measured at
+7dBm input power and should be 32.3 to 32.5dBm with a 3.5 volt supply. This condition
will yield typically 50dBc ACPR1 and 60dBc ACPR2 at 28.5dBm output power and a 3.5 volt
supply using a CDMA waveform. If a greater than 50 ohm impedance transmission line is
used to conserve space, transition the line to 50 ohms slightly prior to the optimum tuning
point to avoid undesirable effects from the otherwise residual inductance following the
tuning elements. Once the optimum tuning point has been established this remains fixed for
all other amplifiers. For the dc bias injection circuit choose an inductor with a maximum
series resistance rating of less than 0.15 ohms for best efficiency and overall performance
versus supply voltage. The two 1.5uF tantalum bypass capacitors chosen for this circuit are
low ESR type capacitors with a maximum rating of 1.5 ohms. The capacitor ESR is critical
for achieving the best ACPR possible from the amplifier. Other capacitors may be
substituted, although larger values may be necessary to achieve equivalent performance.
These components should be placed at the tie point for VD1 and VD2 and as close to the
amplifier as possible. Finally, connect pins 1-3 using one solid metal pad as opposed to
three individual pads for each pin.
Same as pin 1.
Same as pin 1.
Place component C12 ≤ 0.080 inches from the package pin.
Connect pin immediately to the package base solder pad.
Place components R1 and C11 ≤ 0.080 inches from the package pin.
Same as pin 5.
The amplifier input is optimally matched to 50 ohms by locating capacitor C2 at a distance
of 0.138 inches from the package pin. If it is not possible to obtain this separation, adjust
the value of inductor L1 to compensate and obtain the desired match.
Same as pin 5.
Place component C3 ≤ 0.080 inches from the package pin. The dc resistance of inductor L2
should be ≤ 0.5 ohms to obtain optimum amplifier performance. Also, connect VD1 and
VD2 at the board component surface and route VG1 and VG2 bias lines to other conductor
layers to minimize any additional ohmic losses on the drain supply line.
Connect to a low impedance negative voltage power supply for stage 2 current control.
From pinchoff, adjust VG2 voltage to achieve 155mA of stage 2 current, ID2. This current is
optimum for high power CDMA operation up to 28.5dBm output power. For improved
performance, adjust to lower current for low power CDMA and analog modes of operation.
Since both stage 1 and stage 2 drains contribute to the total amplifier current the first
stage must be pinched off while adjusting VG2 for a specific ID2 current. A pinchoff
condition is achieved by applying -2.0 to -5.0 volts to the gate pins, VG1 and VG2.
Connect to a low impedance negative voltage power supply for stage 1 current control, ID1.
From pinchoff, adjust VG1 voltage to achieve 35mA of stage 1 current.
The solder pad for this package should be 0.210 inches square. Fill the pad with several
plated-thru vias connecting the pad surface to the RF input and output ground planes.
Insufficient grounding of the package base may cause the amplifier to oscillate or result in
poor amplifier performance.
www.raytheon.com/micro
Characteristic performance data and specifications are subject to change without notice.
Revised March 30, 2000
Page 5
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
5 Page | ||
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