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부품번호 | PALCE20V8H-20PI4 기능 |
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기능 | EE CMOS 24-Pin Universal Programmable Array Logic | ||
제조업체 | Advanced Micro Devices | ||
로고 | |||
20V8
PALCE20V8
Flash Erasable,
Reprogrammable CMOS PAL Device
Features
• Active pull-up on data input pins
• Low power version (20V8L)
— 55 mA max. commercial (15, 25 ns)
— 65 mA max. military/industrial
(15, 25 ns)
• Standard version has low power
— 90 mA max. commercial
(15, 25 ns)
— 115 mA max. commercial (10 ns)
— 130 mA max. military/industrial (15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• QSOP package available
— 10, 15, and 25 ns com’l version
— 15, and 25 ns military/industrial versions
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.
Logic Block Diagram (PDIP/CDIP/QSOP)
GND
12
I10
11
I9
10
I8 I7 I6
9 87
I5 I4
65
I3 I2 I1 CLK/I0
4 3 21
PROGRAMMABLE
AND ARRAY
(64 x 40)
8 8 8 88 8 8
8
MUX
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
MUX
13 14
15
16
17
18
OE/I11
I12
I/O0
I/O1
I/O2
I/O3
PAL is a registered trademark of Advanced Micro Devices, Inc.
19
I/O4
20 21 22 23 24
I/O5 I/O6 I/O7 I13 VCC
20V8–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03026 Rev. **
Revised March 26, 1997
PALCE20V8
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
VOH
VOL
VIH
VIL[4]
IIH
IIL[5]
ISC
ICC
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
VCC = Min.,
VIN = VIH or VIL
IOH = −3.2 mA
IOH = −2 mA
Com’l
Mil/Ind
VCC = Min.,
VIN = VIH or VIL
IOL = 24 mA
IOL = 12 mA
Com’l
Mil/Ind
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
Input or I/O HIGH Leakage 3.5V < VIN < VCC
Current
Input or I/O LOW Leakage
Current
Output Short Circuit Current
Operating Power Supply
Current
0V < VIN < VIN (Max.)
VCC = Max., VOUT = 0.5V[6,7]
VCC = Max.,
VIL = 0V, VIH = 3V,
Output Open,
f = 15 MHz
(counter)
5, 7, 10 ns
15, 25 ns
15L, 25L ns
10, 15, 25 ns
Com’l
Mil/Ind
15L, 25L ns
Mil/Ind
Min.
2.4
2.0
−0.5
−30
Max. Unit
V
0.5 V
V
0.8 V
10 µA
−100 µA
−150
115
90
55
130
65
mA
mA
mA
mA
mA
mA
Capacitance[7]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
Typ.
5
5
Unit
pF
pF
Endurance Characteristics[7]
Parameter
Description
Test Conditions
Min. Max.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions 100
Cycles
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VIL (Min.) is equal to −3.0V for pulse durations less than 20 ns.
5. The leakage current is due to the internal pull-up resistor on all pins.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03026 Rev. **
Page 4 of 14
4페이지 PALCE20V8
Military Switching Characteristics[2]
Parameter
tPD
tPZX
tPXZ
tEA
tER
tCO
tS
tH
tP
tWH
tWL
fMAX1
fMAX2
fMAX3
tCF
tPR
Description
Input to Output
Propagation Delay[8]
OE to Output Enable
OE to Output Disable
Input to Output Enable Delay[7]
Input to Output Disable Delay[7,9]
Clock to Output Delay[8]
Input or Feedback Set-Up Time
Input Hold Time
External Clock Period (tCO + tS)
Clock Width HIGH[7]
Clock Width LOW[7]
External Maximum Frequency
(1/(tCO + tS)[7,10]
Data Path Maximum Frequency
(1/(tWH + tWL))[7, 11 ]
Internal Feedback Maximum
Frequency (1/(tCF + tS))[7,12]
Register Clock to
Feedback Input[7, 13]
Power-Up Reset Time[7]
Shaded area contains preliminary information.
20V8−10
Min. Max.
1 10
20V8−15
Min. Max.
1 15
20V8−25
Min. Max.
1 25
Unit
ns
10 15 20 ns
10 15 20 ns
10 15 25 ns
10 15 25 ns
1 10 1 12 1 20 ns
10 12 20 ns
0 0 0 ns
20 24 40 ns
8 10 15 ns
8 10 15 ns
50 41.7 25 MHz
62.5 50 33.3 MHz
62.5 50 33.3 MHz
6 8 10 ns
1 1 1 µs
Document #: 38-03026 Rev. **
Page 7 of 14
7페이지 | |||
구 성 | 총 14 페이지수 | ||
다운로드 | [ PALCE20V8H-20PI4.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
PALCE20V8H-20PI | EE CMOS 24-Pin Universal Programmable Array Logic | Advanced Micro Devices |
PALCE20V8H-20PI4 | EE CMOS 24-Pin Universal Programmable Array Logic | Advanced Micro Devices |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |