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PALCE20V8Q-15JC5 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 PALCE20V8Q-15JC5
기능 EE CMOS 24-Pin Universal Programmable Array Logic
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PALCE20V8Q-15JC5 데이터시트, 핀배열, 회로
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all GAL
20V8/As
s Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability
s High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
s Direct plug-in replacement for a wide range of
24-pin PAL devices
s Programmable enable/disable control
s Outputs individually programmable as
registered or combinatorial
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the
user’s design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
BLOCK DIAGRAM
s Peripheral Component Interconnect (PCI)
compliant
s Preloadable output registers for testability
s Automatic register reset on power-up
s Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and func-
tional yields and high reliability
s Programmable output polarity
s 5-ns version utilizes a split leadframe for
improved performance
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
I1 – I10
10
CLK/I0
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
Input
Mux.
OE/I11 I12 I/O0 I/O1 I/O2 I/O4 I/O4 I/O5 I/O6 I/O7 I13
Publication# 16491 Rev. D Amendment /0
Issue Date: February 1996
16491D-1
2-155




PALCE20V8Q-15JC5 pdf, 반도체, 판매, 대치품
AMD
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight
independently configurable macrocells (MC0..MC7).
Each macrocell can be configured as a registered out-
put, combinatorial output, combinatorial I/O, or dedi-
cated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complemen-
tary outputs to provide user-programmable input signal
polarity. Pins 1 and 13 serve either as array inputs or as
clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to VCC or GND.
Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are
automatically configured from the user’s design specifi-
cation, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user’s desired function.
The user is given two design options with the
PALCE20V8. First, it can be programmed as an emu-
lated PAL device. This includes the PAL20R8 series
and most 24-pin combinatorial PAL devices. The PAL
device programmer manufacturer will supply device
codes for the standard PAL architectures to be used
with the PALCE20V8. The programmer will program the
PALCE20V8 to the corresponding PAL device architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed
directly as a PALCE20V8. Here the user must use the
PALCE20V8 device code. This option provides full utili-
zation of the macrocells, allowing non-standard archi-
tectures to be built.
To
Adjacent
Macrocell
11
11
OE
VCC
10
00
0X 01
10
SG1
SL0X
SL1X
DQ
CLK Q
11
0X
10
I/OX
10
11
0X
*SG1
SL0X
From
Adjacent
Pin
* In Macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
Figure 1. PALCE20V8 Macrocell
16491D-4
2-158
PALCE20V8 Family

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PALCE20V8Q-15JC5 전자부품, 판매, 대치품
Power-Up Reset
All flip-flops power up to a logic LOW for predictable sys-
tem initialization. Outputs of the PALCE20V8 depend on
whether they are selected as registered or combinato-
rial. If registered is selected, the output will be HIGH. If
combinatorial is selected, the output will be a function of
the logic.
Register Preload
The register on the PALCE20V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load-
ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Security Bit
A security bit is provided on the PALCE20V8 as a deter-
rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from com-
petitors. The bit can only be erased in conjunction with
the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the
PALCE20V8. It consists of 64 bits of programmable
memory that can contain any user-defined data. The
signature data is always available to the user independ-
ent of the security bit.
AMD
Programming and Erasing
The PALCE20V8 can be programmed on standard logic
programmers. It also may be erased to reset a previ-
ously configured device back to its virgin state. Erasure
is automatically performed by the programming hard-
ware. No special erase operation is required.
Quality and Testability
The PALCE20V8 offers a very high level of built-in qual-
ity. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming and post-programming functional yields in
the industry.
Technology
The high-speed PALCE20V8H is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
PCI Compliance
The PALCE20V8H-7/10 is fully compliant with the PCI
Local Bus Specification published by the PCI Special In-
terest Group. The PALCE20V8H-7/10’s predictable tim-
ing ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD
and FPGA architectures without predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
PALCE20V8 Family
2-161

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