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PALLV16V8Z-20PI 데이터시트 PDF




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부품번호 PALLV16V8Z-20PI 기능
기능 Low Voltage/ Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
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PALLV16V8Z-20PI 데이터시트, 핀배열, 회로
FINAL
COM’L:-10
IND:-20
PALLV16V8-10 and PALLV16V8Z-20
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = +3.0 V to +3.6 V
x Pin and function compatible with all 20-pin PAL® devices
x Electrically-erasable CMOS technology provides reconfigurable logic and full testability
x Direct plug-in replacement for the PAL16R8 series
x Designed to interface with both 3.3-V and 5-V logic
x Outputs programmable as registered or combinatorial in any combination
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the
exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can
always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate cells
in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The sum
of these products feeds the output macrocell. Each macrocell can be programmed as registered or
combinatorial with an active-high or active-low output. The output configuration is determined by
two global bits and one local bit controlling four multiplexers in each macrocell.
Publication# 17713 Rev: E
Amendment/0
Issue Date: November 1998




PALLV16V8Z-20PI pdf, 반도체, 판매, 대치품
SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for
MC7 and OE the adjacent pin for MC0.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x=0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALLV16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x=0. All eight product terms are available to
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception
of MC3 and MC4. MC3 and MC4 do not use feedback in this mode. Because CLK and OE are not
used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the
feedback path of MC7, and pin 11 will use the feedback path of MC0.
Combinatorial I/O In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0x=1. Only seven product terms are available
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O
pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as
an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs.
Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x=1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0x=1. The output buffer is disabled. Except for
MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals are
pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
4 PALLV16V8-10 and PALLV16V8Z-20 Families

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PALLV16V8Z-20PI 전자부품, 판매, 대치품
Benefits of Lower Operating Voltage
The PALLV16V8 has an operating voltage range of 3.0V to 3.6 V. Low voltage allows for lower
operating power consumption, longer battery life, and/or smaller batteries for notebook
applications. The PALLV16V8 inputs accept up to 5.5 V, so they are safe for mixed voltage design.
Because power is proportional to the square of the voltage, reduction of the supply voltage from
5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery
life for portable applications. Lower power consumption can also be used to reduce the size and
weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise
generation and provides a less hostile environment for board design. A lower operating voltage
also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALLV16V8 will depend on whether they are selected as registered or combinatorial. If registered
is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of
the logic.
Register Preload
The register on the PALLV16V8 can be preloaded from the output pins to facilitate functional testing
of complex state machine designs. This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a desired state. In addition,
transitions from illegal states can be verified by loading illegal states and observing proper
recovery.
The preload function is not disabled by the security bit. This allows functional testing after the
security bit is programmed.
Security Bit
A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. However, programming and
verification are also defeated by the security bit. The bit can only be erased in conjunction with
the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the PALLV16V8 device. It consists of 64 bits of
programmable memory that can contain user-defined data. The signature data is always available
to the user independent of the security bit.
Programming and Erasing
The PALLV16V8 can be programmed on standard logic programmers. It also may be erased to reset
a previously configured device back to its unprogrammed state. Erasure is automatically performed
by the programming hardware. No special erase operation is required.
PALLV16V8-10 and PALLV16V8Z-20 Families
7

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PALLV16V8Z-20PI

Low Voltage/ Zero Power 20-Pin EE CMOS Universal Programmable Array Logic

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