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부품번호 PALLV22V10-15JI 기능
기능 Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device
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PALLV22V10-15JI 데이터시트, 핀배열, 회로
PALLV22V10 COM'L: -7/10/15
PALLV22V10Z
IND: -15
IND: -25
PALLV22V10 and PALLV22V10Z Families
Low-Voltage (Zero Power) 24-Pin EE CMOS
Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = + 3.0 V to 3.6 V
x Commercial and industrial operating temperature range
x 7.5-ns tPD
x Electrically-erasable technology provides reconfigurable logic and full testability
x 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x Varied product term distribution allows up to 16 product terms per output for complex
functions
x Global asynchronous reset and synchronous preset for initialization
x Power-up reset for initialization and register preload for testability
x Extensive third-party software and programmer support
x 24-pin SKINNY DIP and 28-pin PLCC packages save space
GENERAL DESCRIPTION
The PALLV22V10 is an advanced PAL® device built with low-voltage, high-speed, electrically-
erasable CMOS technology.
The PALLV22V10Z provides low voltage and zero standby power. At 30 µA maximum standby
current, the PALLV22V10Z allows battery powered operation for an extended period.
The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of
products. The PAL device is a programmable AND array driving a fixed OR array. The AND array
is programmed to create custom product terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to 16
across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell.
Each macrocell can be programmed as registered or combinatorial, and active high or active low.
The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 18956 Rev: F
Amendment/0
Issue Date: September 2000




PALLV22V10-15JI pdf, 반도체, 판매, 대치품
AR
DQ
CLK Q
SP
S0 = 0
S1 = 0
S0 = 0
S1 = 1
a. Registered/active low
S0 = 1
AR S1 = 0
b. Combinatorial/active low
S0 = 1
S1 = 1
DQ
CLK Q
SP
c. Registered/active high
d. Combinatorial/active high
Figure 2. Macrocell Configuration Options
18956D-005
Programmable Three-State Outputs
Each output has a three-state output buffer with three-state control. A product term controls the
buffer, allowing enable and disable to be a function of any product of device inputs or output
feedback. The combinatorial output provides a bi-directional I/O pin, and may be configured as
a dedicated input if the buffer is always disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high or active low, either to match output
signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered
and combinatorial outputs. Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same polarity, the output is
programmed to be active high (S0 = 1).
Preset/Reset
For initialization, the PALLV22V10 has additional preset and reset product terms. These terms are
connected to all registered outputs. When the synchronous preset (SP) product term is asserted
high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition.
When the asynchronous reset (AR) product term is asserted high, the output registers will be
immediately loaded with a LOW independent of the clock.
4 PALLV22V10 and PALLV22V10Z Families

4페이지










PALLV22V10-15JI 전자부품, 판매, 대치품
LOGIC DIAGRAM
CLK/I0 1
(2)
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
0
1
9
10
20
I1 2
(3)
21
I2 3
(4)
33
34
I3 4
(5)
48
49
I4 5
(6)
65
66
I5 6
(7)
82
83
I6 7
(9)
97
98
I7 8
(10)
110
111
121
I8 9
(11)
122
130
I9
10
(12)
I 10 11
(13)
GND 12
(14)
131
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
AR
SP
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
10
11
00
01
0
1
D AR Q
Q
SP
0
1
10
11
00
01
24
(28) VCC
23 I/O9
(27)
22 I/O8
(26)
21 I/O 7
(25)
20 I/O 6
(24)
19 I/O5
(23)
18 I/O 4
(21)
17 I/O3
(20)
16 I/O2
(19)
15 I/O 1
(18)
14 I/O 0
(17)
13 I11
(16)
18956D-006
PALLV22V10 and PALLV22V10Z Families
7

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