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PBL385711NS 데이터시트 PDF




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부품번호 PBL385711NS 기능
기능 High current Speech and Line interface Circuit
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PBL385711NS 데이터시트, 핀배열, 회로
PBJLun3e81597991
PBL 385 71
High current Speech and
Line interface Circuit
Description.
Key features.
PBL 38571 is a monolithic integrated speech transmission circuit for use in
• Minimum number of external
electronic telephones and as DECT line interface with balanced in - and output. It is
components, 5 capacitors and 10
designed to accomodate either a low impedance dynamic microphone or an electret
resistors.
microphone that can be supplied from the circuits own DC - supply. A signal summing • Easy adaption to various market
point at the transmitter input is available. An internally preset line length
needs.
compensation can be adjusted with external resistors to fit into different current feed • Mute control input for operation with
systems as for ex. 48 V, 2 x 200 ohms, 48 V, 2 x 400 ohms and 48 V, 2 x 800
DTMF - generator.
ohms.The line regulation can be shut off in low mode. Application dependent para-
• Transmitter and receiver gain
meters such as line balance, side tone level, transmitter and receiver gains and
regulation for automatic loop loss
frequency responces are set independently by external components which means an
compensation. Disconnectable.
easy adaption to various market needs. The setting of the parameters, if carried out in • Extended current and voltage range
certain order will counteract the interaction between the settings. It features high line
5 - 130 mA, down to 2 V.
current capability on a small footprint. Function compatible with the PBL 3781 family • Differential microphone input for
of speech circuits.
good balance to ground.
• Balanced receiver output stage.
• In 16 - pin DIP and SO BW batwing
packages.
• Short start up time.
• Excellent RFI performance.
10
AM
11
1
PBL 385 71
AT AR
15
87 9 3
2
4,5, 16
12,13.
14 + 6
REC
Mute
(active low)
4
2
3
+
1
Telephone
line
16-pin plastic BW SO
1. Impedance to the line and radio interference suppression
2. Transmitter gain and frequency responce network
3. Receiver gain and frequency responce network
4. Sidetone balance network
Figure 1. Functional diagram.
16-pin plastic BW DIP
1




PBL385711NS pdf, 반도체, 판매, 대치품
PBL 385 71
+L 1
TO 2
TI 3
-L 4
-L 5
+C 6
Mute 7
GR 8
16 RE 2
15 RE 1
14 RI
13 -L
12 -L
11 M2
10 M1
9 MO
16-pin BW DIP
Figure 5. Pin configurations.
+L 1
TO 2
TI 3
-L 4
-L 5
+C 6
Mute 7
GR 8
16 RE2
15 RE1
14 RI
13 -L
12 -L
11 MI
10 MI
9 MO
16-pin BW SO
Pin Descriptions
Refer to figure 5.
Pin Name
1 +L
Function
Output of the transmitter amplifier. Connected to the line through a polarity guard diode bridge.
2 TO
Output of the transmitter amplifier. Connected through a resistor of 47 to 100 ohm to -L,
sets the DC-resistance of the circuit. The output has a low ac. impedance and the signal is used
to drive a side tone balancing network.
3 TI
Input of transmitter amplifier. Input impedance 17 kohm ± 20 %.
}4,12
-L
5,13
Negative power terminal, connected to the line through a polarity guard diode bridge.
6 +C
7 Mute
8 GR
9 MO
}10 MI 1
11 MI 2
14 RI
}15 RE 1
16 RE 2
Positive power supply terminal for most of the circuitry inside the PBL 385 71 (about 1 mA current
consumption). The +C pin should be connected to a decoupling capacitor of 47 µF to 150 µF.
Mute input. Maximum voltage (to mute) is 0.3 V, current sink requirement of external driver is 100 µA.
Input for the gain regulation control circuitry.
Output of the microphone amplifier.
Inputs of the microphone amplifier. Input impedance 1.7 kohm ± 20%.
Input of receiver amplifier. Input impedance is 38 kohm ± 20 %.
Receiver amplifier outputs. Output impedance approximately 3 ohms.
4

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PBL385711NS 전자부품, 판매, 대치품
PBL 385 71
PBL
38571 constant
current
generator
DC
( ref. 1.2V )
9
DC-
load
ref. minus
a diode 0.5V
AC-
load
DC-load = R4+R5
AC-load = R4+R5//ZTI
(a)
9
PBL 38571
10
M
11 +
Dynamic
microphone
(b)
R
C+
(c)
9
6
PBL 38571
10
M
11 +
Balanced electret microphone.
An additional RC filterlink is
recommended if pin 6 is used
as a supply.
6 PBL 38571
9
10
M
11 +
Unbalanced electret
mic. with balanced
signal, DC-supply from
pin 6.
Figure 9. Microphone amplifier output clipping.
Figure 10. Microphone solutions.
Transmitter amplifier
The transmitter amplifier in PBL38571 consists of three stages. The first stage is an amplitude limiter for the input signal at TI, in
order to prevent the transmitted signal to exceed a certain set level and cause distortion. The second stage amplifies further the signal
from the first and adds it to a DC level from an internal DC-regulation loop in order to give the required DC characteristic to the telephone
set. The output of this stage is TO. The third stage is a current generator that presents a high impedance towards the line and has its
gain from TO to +L. The gain of this amplifier is ZL/R6 where ZL is the impedance across the telephone line. Hence, the absolute
maximum signal amplitude that can be transmitted to the line undistorted is dependent of R6. (amplitude limiting)
The transmitter gain and frequency response is set by the RC-network between the pins 9 and 3. See fig.11. The capacitor for
cutting the high end of frequency band is best to be placed directly at the microphone where it also will act as a RFI suppressor. The
input signal source impedance to the transmitter amplifier input TI should be reasonably low in order to keep the gain spread down,
saying that R4//R5 (see fig. 4) must be at least a factor 5 lower than the ZTin. Observe that the capacitor C1 should have a reasonably
good temperature behaviour in order to keep the impedance rather constant. The V+C´s influence on the transmitter DC-characteristic
is shown in the fig.8 (DC-characteristic), therefore the transmitter gain would change if the transmitted signal gives reason to an ac-
voltage leak signal across C1 since this is a feedback point. If the transmitter has an unacceptable low sving to the line at low line
currents <10mA the first step should be to examine if the circuits DC characteristic can be adjusted upwards.
How to calculate the gains in the transmitter channel.
See fig. 2 and 4.
Microphone amplifiers first stage 19 dB.
Microphone amplifiers regulated second stage 10.5 dB - 15.5 dB
Regulation interval 10.5 - 15.5 dB
low gain 19.0 + 10.5 dB = 29.5 dB
high gain 19.0 + 15.5 dB = 34.5 dB
V 2 = RM GM R 5 GTX Rload
V 3 Zmic + RM
R4 +R5
R6
RM = Microphone amplifier input resistance
Rload = Rline // Rtelephone
ex. calculate the gain of the transmitter stage GTX at 0 - line length:
43 = 20 log( (1.7 / /2.7)k ) + 29.5 + 20 log( (17 / /22)k ) + GTX + 20 log( 600/ /910)
350Ω + (1.7 / /2.7)k
18k + (17 / /22)k
75
43 = −2.51+ 29.5 9.17 + GTX + 13.66
GTX = 11.52dB
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부품번호상세설명 및 기능제조사
PBL385711NS

High current Speech and Line interface Circuit

Ericsson
Ericsson

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