QL2009-2PQ208I Datasheet PDF - ETC
| Part Number | QL2009-2PQ208I | |
| Description | 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility | |
| Manufacturers | ETC | |
| Logo |  |
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There is a preview and QL2009-2PQ208I download ( pdf file ) link at the bottom of this page. Total 12 Pages | ||
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QL2009
3.3V and 5.0V pASIC® 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
… 9,000
usable ASIC gates,
225 I/O pins
QL2009
Block Diagram
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
-3-layer metal ViaLink® process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
3
672
Logic
Cells
3-35
|
| |
 
QL2009
PINOUT DIAGRAM
256-PIN PBGA
pASIC
QL2009-1PB256C
TOP
19 17 15 13 11 9 7 5 3 1
PIN A1
CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
BOTTOM
3
3-39
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for QL2009-2PQ208I electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ QL2009-2PQ208I.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| QL2009-2PQ208C | The function is 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility. ETC | |
| QL2009-2PQ208I | The function is 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility. ETC | |
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