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기능 16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM
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QL4016-4PLI 데이터시트, 핀배열, 회로
QL4016 QuickRAM Data Sheet
• • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
Device Highlights
High Performance & High Density
16,000 Usable PLD Gates with 118 I/Os
300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
High Speed Embedded SRAM
10 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
5 ns access times, each port independently
accessible
Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
10
RAM
Blocks
320
High Speed
Logic Cells
Interface
Figure 1: QuickRAM Block Diagram
© 2002 QuickLogic Corporation
www.quicklogic.com
1




QL4016-4PLI pdf, 반도체, 판매, 대치품
QL4016 QuickRAM Data Sheet Rev I
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the
following numbers in the tables provided.
QS
A1
A2
A3
A4
AZ
A5
A6
QS
OP
B1
B2
C1
OZ
C2
MP
MS
QZ
D1
D2
E1
E2
NP
NZ
NS
F1
F2
F3
F4
FZ
F5
F6
QC
QR
Figure 3: QuickRAM Logic Cell
Symbol
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Table 1: Logic Cell
Parameter
Propagation Delays (ns)
Fanout (5)
Combinatorial Delaya
12345
1.4 1.7 1.9 2.2 3.2
Setup Timea
1.7 1.7 1.7 1.7 1.7
Hold Time
0.0 0.0 0.0 0.0 0.0
Clock to Q Delay
0.7 1.0 1.2 1.5 2.5
Clock High Time
1.2 1.2 1.2 1.2 1.2
Clock Low Time
1.2 1.2 1.2 1.2 1.2
Set Delay
1.0 1.3 1.5 1.8 2.8
Reset Delay
0.8 1.1 1.3 1.6 2.6
Set Width
1.9 1.9 1.9 1.9 1.9
Reset Width
1.8 1.8 1.8 1.8 1.8
a. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
4
www.quicklogic.com
© 2002 QuickLogic Corporation

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QL4016-4PLI 전자부품, 판매, 대치품
QL4016 QuickRAM Data Sheet Rev I
Symbol
tI/O
tISU
tIH
tIOCLK
tIORST
tIESU
tIEH
Table 7: I/O Cell Input Delays
Parameter
Propagation Delays (ns)
Fanouta
1 2 3 4 8 10
Input Delay (bidirectional pad)
1.3 1.6 1.8 2.1 3.1 3.6
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock to Q
0.7 1.0 1.2 1.5 2.5 3.0
Input Register Reset Delay
0.6 0.9 1.1 1.4 2.4 2.9
Input Register Clock Enable Set-Up Time
2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
Symbol
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Table 8: I/O Cell Output Delays
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
3 50 75 100 150
Output Delay Low to High
2.1 2.5 3.1 3.6 4.7
Output Delay High to Low
2.2 2.6 3.2 3.7 4.8
Output Delay Tri-state to High
1.2 1.7 2.2 2.8 3.9
Output Delay Tri-state to Low
Output Delay High to Tri-statea
Output Delay High to Tri-statea
1.6 2.0 2.6 3.1 4.2
2.0 -
-
-
-
1.2 -
-
-
-
a. These loads are used for tPXZ (see Figure 5)
1ΚΩ
tPHZ
5 pF
1ΚΩ
tPLZ
5 pF
Figure 5: Loads Used for tPXZ
© 2002 QuickLogic Corporation
www.quicklogic.com
••
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