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PDF QL8050 Data sheet ( Hoja de datos )
| Número de pieza | QL8050 | |
| Descripción | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de QL8050 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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0.18 µ, six layer metal CMOS process
1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O
Up to 4,008 dedicated flip-flops
Up to 55.3 K embedded RAM Bits
Up to 313 I/O
Up to 370 K system gates
IEEE 1149.1 Boundary Scan Testing
Compliant
Low Power Capability
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Up to twenty-four 2,304 bit Dual Port High
Performance SRAM Blocks
Up to 55,296 embedded RAM bits
RAM/ROM/FIFO Wizard for automatic
configuration
Configurable and cascadable
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High performance I/O cell with Tco< 3 ns
Programmable Slew Rate Control
Programmable I/O Standards:
LVTTL, LVCMOS, LVCMOS18, PCI,
GTL+, SSTL2, and SSTL3
Independent I/O Banks capable of
supporting multiple standards in one device
I/O Register Configurations: Input,
Output, Output Enable (OE)
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Multiple dedicated Low Skew Clock
Networks
High drive input-only networks
Quadrant-based segmentable clock networks
User Programmable Phase Locked Loops
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Hardwired DSP building blocks with integrated
Multiply, Add, and Accumulate Functions.
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The QuickLogic products come with secure
ViaLink technology that protects intellectual
property from design theft and reverse
engineering. No external configuration memory
needed; Instant-on at Power-up.
PLL Embedded RAM Blocks
Embeded Computational Units
PLL
Fabric
PLL Embedded RAM Blocks
PLL
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WDATA
WADDR
RAM
Module
(2,304 bits)
RDATA
RADDR
WDATA
RAM
Module
(2,304 bits)
RDATA
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The RAM modules are dual-port, with completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports support asynchronous and synchronous
operation, while the WRITE ports support synchronous operation. Each port has 18 data lines
and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024
words. Depending on the mode selected, however, some higher order data or address lines may
not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read
Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as
a flow-through enable for asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single
modules by connecting corresponding address lines together and dividing the words between
modules.
A similar technique can be used to create depths greater than 512 words. In this case address
signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE
operations. The READ data outputs are multiplexed together using encoded higher READ
address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO
functions) or with data from an external PROM (typically for ROM functions).
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Traditional Programmable Logic architectures do not implement arithmetic functions efficiently
or effectively—these functions require high logic cell usage while garnering only moderate
performance results.
The Eclipse-II architecture allows for functionality above and beyond that achievable using
programmable logic devices. By embedding a dynamically reconfigurable computational unit, the
Eclipse-II device can address various arithmetic functions efficiently. This approach offers greater
performance than traditional programmable logic implementations. The embedded block is
implemented at the transistor level as shown in )LJXUH .
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INPUT
REGISTER
OUTPUT
REGISTER
QE
D
R
Q
D
R
+
-
PAD
OUTPUT ENABLE
REGISTER
EQ
D
R
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The bi-directional I/O pin options can be programmed for input, output, or bi-directional
operation. As shown in )LJXUH , each bi-directional I/O pin is associated with an I/O cell which
features an input register, an input buffer, an output register, a three-state output buffer, an output
enable register, and 2 two-to-one multiplexers. The select lines of the two-to-one multiplexers are
static and must be connected to either Vcc or GND.
For input functions, I/O pins can provide combinatorial, registered data, or both options
simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins
through the input buffer to the array logic. For registered input operation, I/O pins drive the D
input of input cell registers, allowing data to be captured with fast set-up times without consuming
internal logic cell resources. The comparator and multiplexor in the input path allows for native
support of I/O standards with reference points offset from traditional ground.
For output functions, I/O pins can receive combinatorial or registered data from the logic array.
For combinatorial output operation, data is routed from the logic array through a multiplexer to
the I/O pin. For registered output operation, the array logic drives the D input of the output cell
register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a
combinatorial or a registered signal to be driven to the I/O pin. The addition of an output register
will also decrease the Tco. Since the output register does not need to drive the routing the length
of the output path is also reduced.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and
allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually
controlled by the logic cell array or any pin (through the regular routing resources), or it can be
bank-controlled through one of the global networks. The signal can also be either combinatorial
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet QL8050.PDF ] | |
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