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PC-414LVS 데이터시트, 핀배열, 회로
Last Time Buy Notice – Board Products
November 7, 2003
Effective immediately, DATEL, Inc. will be phasing out its line of board-level data acquisition
products. We will accept last time buy orders until February 28, 2004. Final shipments must
be accepted by June 31, 2004. In addition, all repairs and technical support must be concluded
by September 30, 2004. Please contact DATEL Sales as soon as practical to schedule your
order.
If this Notice is received by Purchasing, Materiel or Procurement personnel, we strongly
encourage you to forward this to your Engineering, Administrative and Program colleagues as
soon as practical.
Models to be Discontinued - Essentially all DATEL board-level data acquisition products, all
board-level accessories and all board software are covered in this Notice. This includes:
All ST-xxx model numbers (Multibus I boards, example ST-711)
All PC-xxx model numbers (ISA bus boards, example PC-414)
All DVME-xxx model numbers (VME bus boards, example DVME-628)
All CPCI-xxx model numbers (Compact PCI bus boards, example CPCI-511)
All PCI-xxx model numbers (PCI bus boards, example PCI-416)
Please note that many older ST-xxx, DVME-xxx and PC-xxx boards are already on very
limited availability due to component obsolescence and other manufacturing issues.
Last Time Orders - Customers should contact the DATEL Sales Dept. (Mansfield, MA, USA)
directly to place orders and negotiate delivery schedules. Some products may require minimum
order quantities and/or extended delivery. This varies over time so it is difficult to give an exact
list of such products.
To assure supply, we encourage customers to accept deliveries as soon as practical. As
time passes, customers risk non-availability of an increasing number of products. After the
customer accepts final order acknowledgement, all orders placed will be firm and non-
cancellable.




PC-414LVS pdf, 반도체, 판매, 대치품
PC-414
®®
The FIFO data output may also be routed under host software
control to an on-board parallel data port instead of being sent to
the computer bus. This parallel burst channel data may be read
by an external processor at very high speeds and avoids
possible speed restrictions of the computer bus. The outport
uses a very simple ready/acknowledge transfer handshake which
is adaptable to any remote parallel port including DT Connect®.
See model PC-414COM using a DSP COMM port interface.
The analog section of the PC-414 is optimized for high signal
quality and very low dynamic noise. The PC-414 is ideal as
an FFT “front-end” or DSP quantizer for array processors.
The A/D conversion timing section is designed for accurate multi-
scan data acquisition. Software programmable timers control the
interval between each conversion and each multichannel scan.
A programmable sample counter allows sample blocks of
specified length independent of FIFO length. The timer/counter
section uses a precision on-board crystal clock. Timeout and
sample count activities may be monitored using I/O status
registers and/or programmable interrupts. The interrupt method
may be fully synchronized with software programmable DMA
transfers directly to host computer memory.
S/H - A/D triggering can originate from several sources under
software control. The internal timebase is the normal trigger
source although single conversions or scans may be directly
commanded by host I/O register writes. An external trigger
clock may also be used to precisely synchronize sampling with
external events. This external trigger may start a single
multichannel scan or “N” multiple scans separated by
programmable delays.
Analog sampling can also be level-triggered using an on-board
analog comparator and an external level input. The reference
trigger level to the comparator is derived from an on-board 12-
bit D/A converter. If preferred, the D/A converter may also be
used as a general purpose analog output channel.
The PC-414B, D, F, G, H, K, M, N, and P versions contain five
SMA coaxial signal connectors. Four connectors are for the
sampled analog channels. The fifth connector is used for
external timebase clock input, external analog trigger signal,
or for the analog output. The PC-414E, J, and L versions
contain 25-pin “D” connectors (DB-25S). The burst channel
parallel port uses an internal dual row header.
The computer interface conforms to the PC-AT bus structure.
All data transfers (control, status, and A/D data) use 16-bit
transfers. Interrupt level selection is done via software.
Interrupt servicing is generated for a variety of reasons such
as A/D data read, DMA terminal count, sample count
reached, FIFO half-full, or FIFO full.
A/D output data coding is right-justified two’s complement with
sign extension, if desired, straight binary coding can also be
selected making it directly compatible with high level computer
languages such as “C”, Visual C++, Borland C Builder, Visual
Basic, and others.
Software
The PC-414 can be controlled via optional DOS or Windows
NT or 95/98 Control panels, third party software such as
LabVIEW, or user written code in languages such as Visual
C++, Borland C Builder, Visual Basic, etc.
PC-414SET
An MS-DOS based menu driven acquisition
program. Includes setup and configuration
functions, data acquisition via interrupt and DMA,
D/A and counter timer control. Software also
includes A/D and D/A calibration procedures.
• Automatically configures to the display
adapter, CPU, and mouse
• Sets the I/O base address
• Initializes the interrupt and DMA systems
and D/A output
• Allocates base or extended memory
• Performs self-test and A/D-D/A calibration
• Configures A/D sample rate, frame rate,
and sample counter
• Selects trigger mode and DMA or I/O block
transfer
• Selects disk file output format to integer
binary, float binary, or ASCII float
• Saves data to base memory, extended
memory, or disk
• Full source code in “C” and assembly is
available
• MS-DOS or WINDOWS version (visual
“C” interface)
PC-414SRC Source code for PC-414SET, written in C.
PC-414WIN
PC-414NT
A Windows 95/98 or NT GUI control panel
incorporates all the functions of the PC-414.
Functions include configuration and setup,
analog input to file or disk, analog output, analog
and digital triggering, digital I/O, and calibration.
PC-414WINS Source code for PC-414WIN written in
Borland C Builder.
PC-414LV
Bridge driver software to LabVIEW 4.0 and 3.1.
PC-414LVS
Source code for PC-414LV allows users to
reduce high level VI’s to lower level VI’s.
Analog
Inputs
Parallel
Port
Remote receiver
e.g. DSP board,
memory board, etc.
PC-414
Start &
Exit Mode
Host
Memory
PC-414SET
• Window-driven user interface
• Configure hardware
• Start acquisition
• Send data over parallel port
• Store data to memory and /or
disk file
• View data
• Access digital I/O port
• A/D and D/A calibration
• Update D/A
User written
program
Display
Disk
Graphics
Display
D/A
Converter
Figure 2. PC-414SET Software Operation
DATEL, Inc., Mansfield, MA 02048 (USA) Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 Email: [email protected] Internet: www.datel.com
80

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PC-414LVS 전자부품, 판매, 대치품
®®
PC-414
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C, dynamic conditions, gain = 1, unless noted)
ANALOG INPUTS
PC-414L
PC-414M
Number of Channels
Input Configuration
(non-isolated) [Note 19]
Full Scale Input Ranges
(user-selectable) (gain = 1)
[Notes 1 & 16]
Input Overvoltage
(no damage, power on)
Overvoltage Recovery
Time, maximum
Common Mode Voltage
Range, maximum
Input Impedance [Notes 6 &10]
16 Simultaneous
A/D’s
Single Ended
±5 V, ±10 V,
(user selectable)
[Note 13]
±15 V
8 k
4 Simultaneous
A/D’s
Single Ended
±10 V
±12 V
10 M
SAMPLE/HOLD
Acquisition Time
(FSR step to 0.01% of FSR, max.)
Aperture Delay
Aperture Delay Uncertainty
A/D CONVERTER
400 ns
Resolution
Conversion Period
12 bits
2 µs [Note 12]
16 bits
5 µs [Note 12]
SYSTEM DC CHARACTERISTICS [Note 7]
Integral Non-linearity
(LSB of FSR)
Differential Non-linearity
(LSB of FSR)
Full Scale Temperature
Coefficient (LSB per °C)
Zero or Offset
Temperature Coefficient
(LSB per °C)
±2
±1
[Note 10]
[Note 10]
±4
±3
±1
±1
SYSTEM DYNAMIC PERFORMANCE [Note 2]
Throughput to FIFO
(single channel, gain = 1)
Throughput to FIFO
(sequential channels,
gain = 1)
Total Harmonic Distortion
[Note 3]
400 kHz
190 kHz/chan.
-75 dB
200 kHz
200 kHz/chan.
-83 dB
PC-414N
2 Simultaneous
A/D’s
Single Ended
±2.5 V
±15V
10 Mor 50
35 ns
±10 ns
5 ps
14 bits
200 ns [Note 12]
±1
±1
±0.5
±0.5
5 MHz
5 MHz/chan.
-75 dB
PC-414P
4 Simultaneous
A/D’s
Single Ended
±2.5 V or
0 to +5 V
(user selectable)
±7 V
1000
14 bits
400 ns [Note 12]
±3
±1.5
±0.5
±0.5
3 MHz* min.
2.5 MHz/chan.
-75 dB
* The sample rate to published specifications is 3 MHz. The A/D is functional to 5 MHz. Valid data output per channel is delayed
by 4 samples after the start of the sample clock. Please make note of this for products such as the PC-414P, PC-430P, and
DVME-614P which use non-continuous A/D sampling. Data output is pipelined meaning that the first four samples per channel
should be discarded. For all 4 channels, discard 16 samples. The design is intended for semi-continuous sampling of wideband
signals and is less suitable for low speed data acquisition. Approximately 5 dB SFDR improvement can be achieved by directly
connecting an external A/D sample clock. Contact DATEL for details.
DATEL, Inc., Mansfield, MA 02048 (USA) Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 Email: [email protected] Internet: www.datel.com
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