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PDF PC100 Data sheet ( Hoja de datos )
| Número de pieza | PC100 | |
| Descripción | PC100 SDRAM MODULE Preliminary | |
| Fabricantes | Samsung semiconductor | |
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KMM366S1623CT
Preliminary
PC100 SDRAM MODULE
KMM366S1623CT SDRAM DIMM
16Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM366S1623CT is a 16M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
KMM366S1623CT consists of sixteen CMOS 8M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
The KMM366S1623CT is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
FEATURE
• Performance range
Part No.
Max Freq. (Speed)
KMM366S1623CT-G8
125MHz (8ns @ CL=3)
KMM366S1623CT-GH
100MHz (10ns @ CL=2)
KMM366S1623CT-GL
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50
2 DQ0 30 CS0 58 DQ19 86 DQ32 114 CS1 142 DQ51
3 DQ1 31 DU 59 VDD 87 DQ33 115 RAS 143 VDD
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VDD 34 A2 62 *VREF 90 VDD 118 A3 146 *VREF
7 DQ4 35 A4 63 CKE1 91 DQ36 119 A5 147 NC
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
12 VSS 40 VDD 68 VSS 96 VSS 124 VDD 152 VSS
13 DQ9 41 VDD 69 DQ24 97 DQ41 125 CLK1 153 DQ56
14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 *A12 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 DU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
17 DQ13 45 CS2 73 VDD 101 DQ45 129 CS3 157 VDD
18 VDD 46 DQM2 74 DQ28 102 VDD 130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48 DU 76 DQ30 104 DQ47 132 *A13 160 DQ62
21 *CB0 49 VDD 77 DQ31 105 *CB4 133 VDD 161 DQ63
22 *CB1 50 NC 78 VSS 106 *CB5 134 NC 162 VSS
23 VSS 51 NC 79 CLK2 107 VSS 135 NC 163 CLK3
24 NC 52 *CB2 80 NC 108 NC 136 *CB6 164 NC
25 NC 53 *CB3 81 WP 109 NC 137 *CB7 165 **SA0
26 VDD 54 VSS 82 **SDA 110 VDD 138 VSS 166 **SA1
27 WE 55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
28 DQM0 56 DQ17 84 VDD 112 DQM4 140 DQ49 168 VDD
PIN NAMES
Pin Name
Function
A0 ~ A11
Address input (Multiplexed)
BA0 ~ BA1 Select bank
DQ0 ~ DQ63 Data input/output
CLK0 ~ CLK3 Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS3 Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
DQM0 ~ 7
DQM
VDD Power supply (3.3V)
VSS Ground
*VREF
Power supply for reference
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
WP Write protection
DU Don′t use
NC No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 1 June 1998
1 page  
KMM366S1623CT
Preliminary
PC100 SDRAM MODULE
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS
Latency
Operating current
(one Bank Active)
Burst length =1
ICC1 tRC ≥ tRC(min)
IOL = 0 mA
Precharge standby current in
power-down mode
Precharge standby current in
non power-down mode
ICC2P CKE ≤ VIL(max), tCC = 15ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P CKE ≤ VIL(max), tCC = 15ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Operating current
(Burst mode)
IOL = 0 mA
ICC4
Page burst
2Banks activated
tCCD = 2CLKs
3
2
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
Version
-8 -H -L
760 720 720
16
16
192
96
32
32
320
160
920 760 760
760 760 720
2,000
16
Unit Note
mA 1
mA
mA
mA
mA
mA
mA 1
mA 2
mA
REV. 1 June 1998
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PC100.PDF ] | |
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