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PDF PXA270 Data sheet ( Hoja de datos )
| Número de pieza | PXA270 | |
| Descripción | Electrical/ Mechanical/ and Thermal Specification | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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Intel® PXA270 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
n High-performance processor:
— Intel XScale® microarchitecture with
Intel® Wireless MMX™ Technology
— 7 Stage pipeline
— 32 KB instruction cache
— 32 KB data cache
— 2 KB “mini” data cache
— Extensive data buffering
n 256 Kbytes of internal SRAM for high
speed code or data storage preserved
during low-power states
n High-speed baseband processor interface
(Mobile Scalable Link)
n Rich serial peripheral set:
— AC’97 audio port
— I2S audio port
— USB Client controller
— USB Host controller
— USB On-The-Go controller
— Three high-speed UARTs (two with
hardware flow control)
— FIR and SIR infrared communications
port
n Hardware debug features — IEEE JTAG
interface with boundary scan
n Hardware performance-monitoring
features with on-chip trace buffer
n Real-time clock
n Operating-system timers
n LCD Controller
n Universal Subscriber Identity Module
interface
n Low power:
— Wireless Intel Speedstep® Technology
— Less than 500 mW typical internal
dissipation
— Supply voltage may be reduced to
0.85 V
— Four low-power modes
— Dynamic voltage and frequency
management
n High-performance memory controller:
— Four banks of SDRAM: up to 104 MHz
@ 2.5V, 3.0V, and 3.3V I/O interface
— Six static chip selects
— Support for PCMCIA and Compact
Flash
— Companion chip interface
n Flexible clocking:
— CPU clock from 104 to 624 MHz
— Flexible memory clock ratios
— Frequency changes
— Functional clock gating
n Additional peripherals for system
connectivity:
— SD Card / MMC Controller (with SPI
mode support)
— Memory Stick card controller
— Three SSP controllers
— Two I2C controllers
— Four pulse-width modulators (PWMs)
— Keypad interface with both direct and
matrix keys support
— Most peripheral pins double as GPIOs
Order Number 280002-002
1 page  
Intel® PXA270 Processor
Contents
Tables
6-11 32-Bit Non-burst ROM, SRAM, or Flash Read Timing .....................................6-20
6-12 32-Bit Burst-of-Eight ROM or Flash Read Timing ............................................6-21
6-13 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing..........6-22
6-14 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing ....................................6-23
6-15 Synchronous Flash Burst-of-Eight Read Timing ..............................................6-26
6-16 Synchronous Flash Stacked Burst-of-Eight Read Timing ................................6-27
6-17 First-Access Latency Configuration Timing......................................................6-28
6-18 Synchronous Flash Burst Read Example.........................................................6-30
6-19 32-Bit Flash Write Timing .................................................................................6-31
6-20 32-Bit Stacked Flash Write Timing ...................................................................6-32
6-21 16-Bit Flash Write Timing .................................................................................6-33
6-22 32-Bit SRAM Write Timing ...............................................................................6-35
6-23 16-bit SRAM Write for 4/2/1 Byte(s) Timing .....................................................6-36
6-24 32-Bit VLIO Read Timing .................................................................................6-38
6-25 32-Bit VLIO Write Timing..................................................................................6-39
6-26 Expansion-Card Memory or I/O 16-Bit Access Timing.....................................6-41
6-27 Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ............6-42
6-28 LCD Timing Definitions.....................................................................................6-43
6-29 SSP Master Mode Timing Definitions...............................................................6-44
6-30 SSP Slave Mode Transmitting Data to an External Peripheral ........................6-44
6-31 SSP Slave Mode Receiving Data from External Peripheral .............................6-45
6-32 JTAG Boundary-Scan Timing...........................................................................6-46
1-1 Supplemental Documentation ............................................................................1-2
3-1 Processor Material Properties ............................................................................3-7
4-1 Pin Usage Summary ........................................................................................4-10
4-2 Pin Usage and Mapping Notes.........................................................................4-27
4-3 Signal Types.....................................................................................................4-28
4-4 Memory Controller Pin Reset Values ...............................................................4-28
4-5 Discrete (13x13 VF-BGA) Power Supply Pin Summary...................................4-29
5-1 Absolute Maximum Ratings................................................................................5-1
5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2
5-3 Memory Voltage and Frequency Electrical Specifications .................................5-4
5-4 Core Voltage and Frequency Electrical Specifications.......................................5-4
5-5 Internally Generated Power Domain Descriptions .............................................5-6
5-6 Core Voltage Specifications For Lower Power Modes .......................................5-6
5-7 Power-Consumption Specifications....................................................................5-7
5-8 Standard Input, Output, and I/O Pin DC Operating Conditions ..........................5-8
5-9 Typical 32.768-kHz Crystal Requirements .........................................................5-9
5-10 Typical External 32.768-kHz Oscillator Requirements ....................................5-11
5-11 Typical 13.000-MHz Crystal Requirements......................................................5-11
5-12 Typical External 13.000-MHz Oscillator Requirements....................................5-12
5-13 CLK_PIO Specifications ...................................................................................5-12
5-14 CLK_TOUT Specifications ...............................................................................5-12
5-15 48 MHz Output Specifications ..........................................................................5-13
6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions ..........................6-1
6-2 Power-On Timing Specifications (OSCC[CRI] = 0) ............................................6-3
6-3 Hardware Reset Timing Specifications (OSCC[CRI] = 0) ..................................6-4
6-4 Hardware Reset Timing Specifications (OSCC[CRI] = 1) .................................6-5
Electrical, Mechanical, and Thermal Specification
v
5 Page 
Functional Overview
2
The Intel® PXA270 processor is an integrated system-on-a-chip microprocessor for high
performance, dynamic, low-power portable handheld and hand-set devices as well as embedded
platforms. It incorporates the Intel XScale® technology which complies with the ARM* version
5TE instruction set (excluding floating-point instructions) and follows the ARM* programmer’s
model. The PXA270 processor also provides Intel® Wireless MMX™ media enhancement
technology, which supports integer instructions to accelerate audio and video processing. In
addition, it incorporates Wireless Intel Speedstep® Technology, which provides sophisticated
power management capabilities enabling excellent MIPs/mW performance.
The PXA270 processor provides a scalable, bi-directional data interface to a cellular baseband
processor, supporting seven logical channels and other features. The operating-system (OS) timer
channels and synchronous serial ports (SSPs) also accept an external network clock input so that
they can be synchronized to the cellular network. The processor also provides a Universal
Subscriber Identity Module* (USIM) card interface.
The PXA270 processor memory interface gives designers flexibility as it supports a variety of
external memory types. The processor also provides four 64 kilobyte banks of on-chip SRAM,
which can be used for program code or multimedia data. Each bank can be configured
independently to retain its contents when the processor enters a low-power mode. An integrated
LCD panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray
scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit color pixels. A 256-byte palette RAM provides flexible
color mapping.
A set of serial devices and general-system resources offers computational and connectivity
capability for a variety of applications. Figure 2-1 shows the block diagram for a typical PXA270
processor system.
Electrical, Mechanical, and Thermal Specification
2-1
11 Page | ||
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| PDF Descargar | [ Datasheet PXA270.PDF ] | |
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