Datasheet.kr   

IDT79R3052E-40MJ 데이터시트 PDF




Integrated Device에서 제조한 전자 부품 IDT79R3052E-40MJ은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 IDT79R3052E-40MJ 자료 제공

부품번호 IDT79R3052E-40MJ 기능
기능 RISControllers
제조업체 Integrated Device
로고 Integrated Device 로고


IDT79R3052E-40MJ 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 23 페이지수

미리보기를 사용할 수 없습니다

IDT79R3052E-40MJ 데이터시트, 핀배열, 회로
Integrated Device Technology, Inc.
IDT79R3051/79R3052
RISControllers
IDT79R3051, 79R3051E
IDT79R3052, 79R3052E
FEATURES:
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
— IDT79R3000A /IDT79R3001 RISC Integer CPU
— R3051 features 4KB of Instruction Cache
— R3052 features 8KB of Instruction Cache
— All devices feature 2kB of Data Cache
— “E” Versions (Extended Architecture) feature full
function Memory Management Unit, including 64-
entry Translation Lookaside Buffer (TLB)
— 4-deep write buffer eliminates memory write stalls
— 4-deep read buffer supports burst refill from slow
memory devices
— On-chip DMA arbiter
— Bus Interface minimizes design complexity
• Single clock input with 40%-60% duty cycle
• 35 MIPS, over 64,000 Dhrystones at 40MHz
• Low-cost 84-pin PLCC packaging that's pin-/package-
compatible with thermally enhanced 84-pin MQUAD.
• Flexible bus interface allows simple, low-cost designs
• 20, 25, 33, and 40MHz operation
• Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point Software
— Page Description Languages
Clk2xIn
Int(5:0)
Clock
Generator
Unit
Master Pipeline Control
BrCond(3:0)
System Control
Coprocessor
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Translation
Lookaside Buffer
(64 entries)
Mult/Div Unit
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
Instruction
Cache
(8kB/4kB)
Data
Cache
(2kB)
4-deep
Write
Buffer
Data Bus
Bus Interface Unit
4-deep
Read
Buffer
DMA
Arbiter
BIU
Control
32
Address/
Data
DMA Rd/Wr SysClk
Ctrl Ctrl
Figure 1. R3051 Family Block Diagram
2874 drw 01
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology, Inc.
5.3
SEPTEMBER 1995
DSC-3000/5
1




IDT79R3052E-40MJ pdf, 반도체, 판매, 대치품
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Clock Generation Unit
The IDT79R3051 family is driven from a single input clock,
capable of operating in a range of 40%-60% duty cycle. On
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in IDT79R3000A and IDT79R3001 based applications.
Instruction Cache
The current family includes two different instruction cache
sizes: the IDT79R3051 family (the IDT79R3051 and
IDT79R3051E) feature 4KB of instruction cache, and the
IDT79R3052 and IDT79R3052E each incorporate 8KB of
Instruction Cache. For all four devices, the instruction cache
is organized as a line size of 16 bytes (four words). This
relatively large cache achieves a hit rate well in excess of 95%
in most applications, and substantially contributes to the
performance inherent in the IDT79R3051 family. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses (rather than virtual addresses), and thus does not
require flushing on context switch.
Data Cache
All four devices incorporate an on-chip data cache of 2KB,
organized as a line size of 4 bytes (one word). This relatively
large data cache achieves hit rates well in excess of 90% in
most applications, and contributes substantially to the perfor-
mance inherent in the IDT79R3051 family. As with the instruc-
tion cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4-
deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.
of the memory system. The write buffers capture and FIFO
processor address and data information in store operations,
and presents it to the bus interface as write transactions at the
rate the memory system can accommodate.
The IDT79R3051/52 read interface performs both single
word reads and quad word reads. Single word reads work with
a simple handshake, and quad word reads can either utilize
the simple handshake (in lower performance, simple sys-
tems) or utilize a tighter timing mode when the memory system
can burst data at the processor clock rate. Thus, the system
designer can choose to utilize page or nibble mode DRAMs
(and possibly use interleaving), if desired, in high-perfor-
mance systems, or use simpler techniques to reduce com-
plexity.
In order to accommodate slower quad-word reads, the
IDT79R3051 family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches. Depending on the cost vs. performance
tradeoffs appropriate to a given application, the system design
engineer could include true burst support from the DRAM to
provide for high-performance cache miss processing, or uti-
lize the read buffer to process quad word reads from slower
memory systems.
SYSTEM USAGE
The IDT79R3051 family has been specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems utilize slow EPROMs, DRAMs, and applica-
tion-specific peripherals. These systems may also typically
contain large, slow Static RAMs, although the IDT79R3051
family has been designed to not specifically require the use of
external SRAMs.
Figure 5 shows a typical system block diagram. Transpar-
ent latches are used to de-multiplex the IDT79R3051/52
address and data busses from the A/D bus. The data paths
between the memory system elements and the R3051 family
A/D bus is managed by simple octal devices. A small set of
simple PALs can be used to control the various data path
elements, and to control the handshake between the memory
devices and the CPU.
Bus Interface Unit
The IDT79R3051 family uses its large internal caches to
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.
The IDT79R3051 family bus interface utilizes a 32-bit
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE signal to de-
multiplex the A/D bus, and simple handshake signals to
process processor read and write requests. In addition to the
read and write interface, the IDT79R3051 family incorporates
a DMA arbiter, to allow an external master to control the
external bus.
The IDT79R3051 family incorporates a 4-deep write buffer
to decouple the speed of the execution engine from the speed
DEVELOPMENT SUPPORT
The IDT79R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through prom monitor support, logic analysis tools, and sub-
system modules.
Figure 7 is an overview of the system development process
typically used when developing IDT79R3051 family-based
applications. The IDT79R3051 family is supported by power-
ful tools through all phases of project development. These
tools allow timely, parallel development of hardware and
software for IDT79R3051/52 based applications, and include
tools such as:
• A program, Cache-3051, which allows the performance of
an IDT79R3051 family based system to be modeled and
understood without requiring actual hardware.
5.3 4

4페이지










IDT79R3052E-40MJ 전자부품, 판매, 대치품
IDT79R3051/79R3052 INTEGRATED RISControllers
System
Architecture
Evaluation
System
Development
Phase
Cache-R305x
Benchmarks
Evaluation Board
Laser Printer System
Software
SABLE Simulator
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScriptPDL
MicroSoft TrueImagePDL
Ada
Hardware
Cache-R305x
Hardware Models
General CAD Tools
RISC Sub-systems
Evaluation Board
Laser Printer System
COMMERCIAL TEMPERATURE RANGE
System
Integration
and Verification
Logic Analysis
Diagnostics
IDT PROM Monitor
Remote Debug
Real-Time OS
In-Circuit Emulator
Figure 7. R3051 Family Development Toolchain
2874 drw 07
5.3 7

7페이지


구       성 총 23 페이지수
다운로드[ IDT79R3052E-40MJ.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
IDT79R3052E-40MJ

RISControllers

Integrated Device
Integrated Device

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵