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IDT79R3081-20FD 데이터시트 PDF




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IDT79R3081-20FD 데이터시트, 핀배열, 회로
IDT79R3081 RISController
Integrated Device Technology, Inc.
IDT79R3081
RISController
with FPA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT 79R3081, 79R3081E
IDT 79RV3081, 79RV3081E
FEATURES
• Instruction set compatible with IDT79R3000A, R3041,
R3051, and R3071 RISC CPUs
• High level of integration minimizes system cost
— R3000A Compatible CPU
— R3010A Compatible Floating Point Accelerator
— Optional R3000A compatible MMU
— Large Instruction Cache
— Large Data Cache
— Read/Write Buffers
• 43VUPS at 50MHz
— 13MFlops
• Flexible bus interface allows simple, low cost designs
• Optional 1x or 2x clock input
• 20 through 50MHz operation
• "V" version operates at 3.3V
• 50MHz at 1x clock input and 1/2 bus frequency only
• Large on-chip caches with user configurability
— 16kB Instruction Cache, 4kB Data Cache
— Dynamically configurable to 8kB Instruction Cache,
8kB Data Cache
— Parity protection over data and tag fields
• Low cost 84-pin packaging
• Superset pin- and software-compatible with R3051, R3071
• Multiplexed bus interface with support for low-cost, low-
speed memory systems with a high-speed CPU
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-deep read buffer supports burst or simple block
reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface can operate at half-processor frequency
R3081 BLOCK DIAGRAM
BrCond(3:2,0)
ClkIn
Clock Generator
Unit/Clock Doubler
Master Pipeline Control
System Control
Coprocessor
(CP0)
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Int(5:0)
Translation
Lookaside Buffer
(64 entries)
Mult/Div Unit
Address Adder
PC Control
Virtual Address
FP Interrupt
Floating Point
Coprocessor
(CP1)
Register Unit
(16 x 64)
Exponent Unit
Add Unit
Divide Unit
Multiply Unit
Exception/Control
Physical Address Bus
Data Bus
32 Configurable
Instruction
Cache
(16kB/8kB)
Configurable
Data
Cache
(4kB/8kB)
Data Bus
36
Parity
Generator
4-deep
Read
Buffer
R3051 Superset Bus Interface Unit
4-deep
Write
Buffer
DMA
Arbiter
BIU
Control
Coherency
Logic
Address/
Data
DMA
Ctrl
Rd/Wr
Ctrl
SysClk Invalidate
Control
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The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
5.5
5.5
SEPTEMBER 1995
DSC-9064/4
1




IDT79R3081-20FD pdf, 반도체, 판매, 대치품
IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
a double frequency clock. The 2x clock mode is provided for
compatiblity with the R3051. The clock generator unit replaces
the external delay line required in R3000A based applications.
Instruction Cache
The R3081 implements a 16kB Instruction Cache. The
system may choose to repartition the on-chip caches, so that
the instruction cache is reduced to 8kB but the data cache is
increased to 8kB. The instruction cache is organized with a
line size of 16bytes (four entries). This large cache achieves
hit rates in excess of 98% in most applications, and substantially
contributes to the performance inherent in the R3081. The
cache is implemented as a direct mapped cache, and is
capable of caching instructions from anywhere within the 4GB
physical address space. The cache is implemented using
physical addresses (rather than virtual addresses), and thus
does not require flushing on context switch.
The instruction cache is parity protected over the instruction
word and tag fields. Parity is generated by the read buffer
during cache refill; during cache references, the parity is
checked, and in the case of a parity error, a cache miss is
processed.
Data Cache
The R3081 incorporates an on-chip data cache of 4kB,
organized as a line size of 4 bytes (one word). The R3081
allows the system to reconfigure the on-chip cache from the
default 16kB I-Cache/4kB D-Cache to 8kB of Instruction and
8kB of Data caches.
The relatively large data cache achieves hit rates in excess
of 95% in most applications, and contributes substantially to
the performance inherent in the R3081. As with the instruction
cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write-through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4-
deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance. Further, support has been provided to allow
hardware based data cache coherency in a multi-master
environment, such as one utilizing DMA from I/O to memory.
The data cache is parity protected over the data and tag
fields. Parity is generated by the read buffer during cache refill;
during cache references, the parity is checked, and in the case
of a parity error, a cache miss is processed.
Bus Interface Unit
The R3081 uses its large internal caches to provide the
majority of the bandwidth requirements of the execution
engine, and thus can utilize a simple bus interface connected
to slower memory devices. Alternately, a high-performance,
low-cost secondary cache can be implemented, allowing the
processor to increase performance in systems where bus
bandwidth is a performance limitation.
As part of the R3051 family, the R3081 bus interface utilizes
a 32-bit address and data bus multiplexed onto a single set of
pins. The bus interface unit also provides an ALE (Address
Latch Enable) output signal to de-multiplex the A/D bus, and
Cache
Data
(32)
Instructions
Condition
Codes
Control Unit
and Clocks
Data Bus
Exponent Part
(11) (11)
(32)
Operands
Register Unit (16 X 64)
Fraction
(11) (53) (53)
A B Result
Exponent
Unit
AB
Add Unit
Divide Unit
(53)
A
(53)
B
Multiply Unit
(53)
A
(53)
B
Figure 5. FPA Functional Block Diagram
5.5
(53)
Result
Round
(56)
Result
(56)
Result
2889 drw 05
4

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IDT79R3081-20FD 전자부품, 판매, 대치품
IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
many general purpose computing applications, such as
ARC compliant systems.
Autonomous multiply and divide operations.The R3051
family features an on-chip integer multiplier/divide unit
which is separate from the other ALU. This allows the CPU
to perform multiply or divide operations in parallel with other
integer operations, using a single multiply or divide
instruction rather than “step” operations.
Integrated write buffer. The R3081 features a four deep
write buffer, which captures store target addresses and
data at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of on-
chip write buffers eliminates the need for the processor to
stall when performing store operations.
Burst read support. The R3051 family enables the system
designer to utilize page mode or nibble mode RAMs when
performing read operations to minimize the main memory
read penalty and increase the effective cache hit rates.
These techniques combine to allow the processor to achieve
over 43 VUPS integer performance, 13MFlops of Linpack
performance, and 70,000 dhrystones without the use of external
caches or zero wait-state memory devices.
The performance differences between the various family
members depends on the application software and the design
of the memory system. The impact of the various cache sizes,
and the hardware floating point, can be accurately modeled
using Cache-3051. Since the R3041, R3051, R3052, R3071,
and R3081 are all pin and software compatible, the system
designer has maximum freedom in trading between
performance and cost. A system can be designed, and later
the appropriate CPU inserted into the board, depending on the
desired system performance.
SELECTABLE FEATURES
The R3081 allows the system designer to configure certain
aspects of operation. Some of these options are established
when the device is reset, while others are enabled via the
Config registers:
BigEndian vs. LittleEndian Byte Ordering. The part can
be configured to operate with either byte ordering. ACE/
ARC systems typically use Little Endian byte ordering.
However, various embedded applications, written originally
for a Big Endian processor such as the MC680x0, are
easier to port to a Big Endian system.
Data Cache Refill of one or four words. The memory
system must be capable of performing four word refills of
instruction cache misses. The R3081 allows the system
designer to enable D-Cache refill of one or four words
dynamically. Thus, specialized algorithms can choose one
refill size, while the rest of the system can operate with the
other.
Half-frequency bus mode. The processor can be
configured such that the external bus interface is at one-
half the frequency of the processor core. This simplifies
system design; however, the large on-chip caches mitigate
the performance impact of using a slower system bus clock.
Slow bus turn-around. The R3081 allows the system
designer to space processor operations, so that more time
is allowed for transitions between memory and the processor
on the multiplexed address/data bus.
Configurable cache. The R3081 allows the system
designer to use software to select either a 16kB Instruction
Cache/4kB Data Cache organization, or an 8kB Instruction/
8kB Data Cache organization.
Cache Coherent Interface. The R3081 has an optional
hardware based cache coherency interface intended to
support multi-master systems such as those utilizing DMA
between memory and I/O.
Optional 1x or 2x clock input. The R3081 can be driven
with an R3051 compatible 2x clock input, or a lower
frequency 1x clock input.
THERMAL CONSIDERATIONS
The R3081 utilizes special packaging techniques to improve
the thermal properties of high-speed processors. Thus, the
R3081 is packaged using cavity down packaging, with an
embedded thermal slug to improve thermal transfer to the
suurrounding air.
The R3081 utilizes the 84-pin MQUAD package (the "MJ"
package), which is an all aluminum package with the die
attached to a normal copper lead-frame mounted to the
aluminum casing. The MQUAD package allows for an efficient
thermal transfer between the die and the case due to the heat
spreading effect of the aluminum. The aluminum offers less
internal resistance from one end of the package to the other,
reducing the temperature gradient across the package and
therefore presenting a greater area for convection and
conduction to the PCB for a given temperature. Even nominal
amounts of airflow will dramatically reduce the junction
temperature of the die, resulting in cooler operation. The
MQUAD package is available at all frequencies, and is pin and
form compatible with the PLCC used for the R3051. Thus,
designers can inter-change R3081s and R3051s in a particular
design, without changing their PC Board.
The R3081 is guaranteed in a case temperature range of
0°C to +85°C. The type of package, speed (power) of the
device, and airflow conditions, affect the equivalent ambient
temperature conditions which will meet this specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
CA) of the given package. The following equation relates
ambient and case temperatures:
TA = TC - P * ØCA
where P is the maximum power consumption at hot
temperature, calculated by using the maximum Icc specification
for the device.
Typical values for ØCA at various airflows are shown in
Table 1.
Note that the R3081 allows the operational frequency to be
turned down during idle periods to reduce power consumption.
This operation is described in the R3081 Hardware User's
Guide. Reducing the operation frequency dramatically reduces
power consumption.
5.5 7

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