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PC97338VJG 데이터시트 PDF




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부품번호 PC97338VJG 기능
기능 ACPI 1.0 and PC98/99 Compliant SuperI/O
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PC97338VJG 데이터시트, 핀배열, 회로
November 1998
PC87338/PC97338
ACPI 1.0 and PC98/99 Compliant SuperI/O
General Description
The PC97338 is a fully ACPI 1.0 and PC98/99 com-
pliant, ISA based Super I/O. It is functionally compat-
ible with the PC87338. It includes a Floppy Disk
Controller (FDC), two Serial Communication Control-
lers (SCC) for UART and Infrared support, one
IEEE1284 compatible Parallel Port, and two general
purpose Chip Select signals for game port support.
The device supports power management as well as
3.3V and 5V mixed operation making it particularly
suitable for notebook and sub-notebook applications.
The PC87338 and PC97338 are fully compliant to the
Plug and Play specifications included in the "Hard-
ware Design Guide for Microsoft Windows 95".
Differences between the PC87338 and PC97338 are
indicated in italics. These differences are summarized
in Appendix A.
Features
s Meets ACPI 1.0 and PC98/99 requirements
s Backward compatible with PC87338
s 100% compatibility with Plug and Play require-
ments specified in the “Hardware Design Guide for
Microsoft Windows 95”, ISA, EISA, and Micro-
Channel architectures
s A special Plug and Play module includes:
Flexible IRQs, DMAs and base addresses
General Interrupt Requests (IRQs) that can be
multiplexed to the ten supported IRQs
Block Diagram
CS1,0
Configuration Input
Signals
Serial Interface
Serial Fast IR
Interface Interface
General
Chip Select
Configuration
Registers
SCC1
(16550 UART)
SCC2
(16550 UART +
INFRARED)
Micro-
processor
Address
Data and
Control
Interrupt
and DMA
Plug and Play
Support
Power-
Down
Logic
IEEE1284
Parallel Port
High Current Driver
Floppy
Drive
Interface
Floppy Disk
Controller (FDC)
with
Digital Data
Separator (DDS)
(Enhanced 8477)
Floppy
Drive
Interface
DMA IRQ IRQ Input
Channels
Signals
Control
Data Handshake
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
© 1998 National Semiconductor Corporation
1
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PC97338VJG pdf, 반도체, 판매, 대치품
Clock
External
Device
Parallel
Port
Connector
Configuration
Selection Logic
Basic Configuration
X1(CLKIN)
CS0,1
MR
AEN
A0-A15
D0-D7
RD
WR
IOCHRDY
ZWS
IRQ3-7, 9-12, 15
TC
DACK0,1,2,3
DRQ0,1,2,3
SIN1
SOUT1
RTS1
BOUT1/DTR1
CTS1
DSR1
DCD1
RI1
IRTX
IRRX1,2
IRSL0-2/ID0-2
PC97338VLJ
SIRQI1,2,3
PC97338VJG
Super I/O
PD0/INDEX
PD1/TRK0
PD2/WP
PD3/RDATA
PD4/DSKCHG
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
SLIN/STEP/ASTRB
STB/WRITE
AFD/DENSEL/DSTRB
INIT/DIR
ACK/DR1
ERR/HDSEL
SLCT/WGATE
PE/WDATA
BUSY/MTR1/WAIT
PNF
BADDR0,1
CFG0
SIN2
SOUT2
RTS2
BOUT2/DTR2
CTS2
DSR2
DCD2
RI2
RDATA
WDATA
WGATE
HDSEL
DIR
STEP
TRK0
INDEX
DSKCHG
WP
IDLE/MTR0,1
DR0,1
DR23
DRV2
DENSEL
Game
Port
EIA
Drivers
IR
Interface
EIA
Drivers
FDC
Connector
External
Power Down
Control
FDC
Configuration
Logic
4
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PC97338VJG 전자부품, 판매, 대치품
3.6.2 The CONFIGURE Command .................................................................................................. 94
3.6.3 The DUMPREG Command ..................................................................................................... 95
3.6.4 The FORMAT TRACK Command ........................................................................................... 96
3.6.5 The INVALID Command ......................................................................................................... 99
3.6.6 The LOCK Command ............................................................................................................ 100
3.6.7 The MODE Command ........................................................................................................... 100
3.6.8 The NSC Command .............................................................................................................. 103
3.6.9 The PERPENDICULAR MODE Command ........................................................................... 103
3.6.10 The READ DATA Command ............................................................................................... 105
3.6.11 The READ DELETED DATA Command ............................................................................. 108
3.6.12 The READ ID Command ..................................................................................................... 109
3.6.13 The READ A TRACK Command ......................................................................................... 110
3.6.14 The RECALIBRATE Command ........................................................................................... 110
3.6.15 The RELATIVE SEEK Command ........................................................................................ 111
3.6.16 The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH
OR EQUAL Commands ...................................................................................................... 112
3.6.17 The SEEK Command .......................................................................................................... 113
3.6.18 The SENSE DRIVE STATUS Command ............................................................................ 114
3.6.19 The SENSE INTERRUPT Command .................................................................................. 114
3.6.20 The SET TRACK Command ............................................................................................... 115
3.6.21 The SPECIFY Command .................................................................................................... 116
3.6.22 The VERIFY Command ...................................................................................................... 118
3.6.23 The VERSION Command ................................................................................................... 119
3.6.24 The WRITE DATA Command ............................................................................................. 120
3.6.25 The WRITE DELETED DATA Command ............................................................................ 121
3.7 EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87338/PC97338 .................................. 121
4.0 Parallel Port
4.1 INTRODUCTION ............................................................................................................................ 123
4.1.1 The Chip Parallel Port Modes ............................................................................................... 123
4.1.2 Device Configuration ............................................................................................................. 123
4.2 STANDARD PARALLEL PORT MODES ........................................................................................ 123
4.2.1 Standard Parallel Port (SPP) Modes Register Set ................................................................ 124
4.2.2 SPP Mode Parallel Port Register Bitmaps ............................................................................ 124
4.2.3 Data Register (DTR), Offset 0 ............................................................................................... 124
4.2.4 Status Register (STR), Offset 1 ............................................................................................. 125
4.2.5 Control Register (CTR), Offset 2 ........................................................................................... 126
4.3 ENHANCED PARALLEL PORT (EPP) MODES ............................................................................. 127
4.3.1 Enhanced Parallel Port (EPP) Modes Register Set .............................................................. 128
4.3.2 EPP Modes Parallel Port Register Bitmaps .......................................................................... 128
4.3.3 SPP or EPP Data Register (DTR), Offset 0 .......................................................................... 129
4.3.4 SPP or EPP Status Register (STR), Offset 1 ........................................................................ 129
4.3.5 SPP or EPP Control Register (CTR), Offset 2 ...................................................................... 129
4.3.6 EPP Address Register, Offset 3 ............................................................................................ 130
4.3.7 EPP Data Port 0, Offset 4 ..................................................................................................... 130
4.3.8 EPP Data Port 1, Offset 5 ..................................................................................................... 130
4.3.9 EPP Data Port 2, Offset 6 ..................................................................................................... 130
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관련 데이터시트

부품번호상세설명 및 기능제조사
PC97338VJG

ACPI 1.0 and PC98/99 Compliant SuperI/O

National Semiconductor
National Semiconductor

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