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PCA2001AA 데이터시트 PDF




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부품번호 PCA2001AA 기능
기능 32 kHz watch circuit with programmable adaptive motor pulse
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PCA2001AA 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCA2000; PCA2001
32 kHz watch circuit with
programmable adaptive motor
pulse
Product specification
Supersedes data of 2003 Feb 04
2003 Dec 17




PCA2001AA pdf, 반도체, 판매, 대치품
Philips Semiconductors
32 kHz watch circuit with programmable
adaptive motor pulse
Product specification
PCA2000; PCA2001
FUNCTIONAL DESCRIPTION
Motor pulse
The motor output supplies pulses of different driving
stages, depending on the torque required to turn on the
motor. The number of different stages can be selected
between three and six. With the exception of the highest
driving stage, each motor pulse (tp in Figs 3 and 6) is
followed by a detection phase during which the motor
movement is monitored, in order to check whether the
motor has turned correctly or not.
If a missing step is detected, a correction sequence is
generated (see Fig.3) and the driving stage is switched to
the next level. The correction sequence consists of two
pulses: first a short pulse in the opposite direction
(0.98 ms, modulated with the maximum duty cycle) to give
the motor a defined position, followed by a motor pulse of
the strongest driving level. Every 4 minutes, the driving
level is lowered again by one stage.
The motor pulse has a constant pulse width. The driving
level is regulated by chopping the driving pulse with a
variable duty cycle. The driving level starts from the
programmed minimum value and increases by 6.25% after
each failed motor step. The strongest driving stage, which
is not followed by a detection phase, is programmed
separately.
Therefore, it is possible to program a larger energy gap
between the pulses with step detection and the strongest,
not monitored, pulse. This might be necessary to ensure a
reliable and stable operation under adverse conditions
(magnetic fields, vibrations). If the watch works in the
highest driving stage, the driving level jumps after the
4-minute period directly to the lowest stage, and not just
one stage lower.
To optimize the performance for different motors, the
following parameters can be programmed:
Pulse width: 0.98 to 7.8 ms in steps of 0.98 ms
Duty cycle of lowest driving level: 37.5% to 56.25% in
steps of 6.25%
Number of driving levels (including the highest driving
level): 3 to 6
Duty cycle of the highest driving level: 75% or 100%
Enlargement pulse for the highest driving level: on or off.
The enlargement pulse has a duty cycle of 25% and a
pulse width which is twice the programmed motor pulse
width. The repetition period for the chopping pattern is
0.98 ms. Figure 4 shows an example of a 3.9 ms pulse.
handbook, full pagewidth
tp
1.96 ms
detection phase
tp 2tp
31.25 ms
0.98 ms
31.25 ms
Fig.3 Correction sequence after failed motor step.
MGW350
2003 Dec 17
4

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PCA2001AA 전자부품, 판매, 대치품
Philips Semiconductors
32 kHz watch circuit with programmable
adaptive motor pulse
Product specification
PCA2000; PCA2001
Time calibration
The quartz crystal oscillator has an integrated capacitance
of 5.2 pF, which is lower than the specified capacitance
(CL) of 8.2 pF for the quartz crystal. Therefore, the
oscillator frequency is typically 60 ppm higher than
32.768 kHz. This positive frequency offset is compensated
by removing the appropriate number of 8192 Hz pulses in
the divider chain (maximum 127 pulses), every
1 or 2 minutes. The time correction is given in Table 1.
After measuring the effective oscillator frequency, the
number of correction pulses must be calculated and stored
together with the calibration period in the OTP memory
(see Section “Programming the memory cells”).
The oscillator frequency can be measured at pad RESET,
where a square wave signal with the frequency of
1----0--1-2----4- × fosc is provided.
This frequency shows a jitter every minute or every two
minutes, depending on the programmed calibration period,
which originates from the time calibration.
Details on how to measure the oscillator frequency and the
programmed inhibit time are given in Section
“Measurement of oscillator frequency and inhibit time”.
Reset
At pin RESET an output signal with a frequency of
1----0--1-2----4- × fosc = 32 Hz is provided.
Connecting pad RESET to VDD stops the motor drive and
opens all four (P1, N1, P2 and N2) driver switches (see
Fig.5). Connecting pad RESET to VSS activates the test
mode. In this mode the motor output frequency is 32 Hz,
which can be used to test the mechanical function of the
watch.
After releasing the pad RESET, the motor starts exactly
one second later with the smallest duty cycle and with the
opposite polarity to the last pulse before stopping.
The debounce time for the RESET function is between
31 and 62 ms.
Programming possibilities
The programming data is stored in OTP cells (EPROM
cells). At delivery, all memory cells are in state 0. The cells
can be programmed to the state 1, but then there is no
more set back to state 0.
The programming data is organized in an array of three
8-bit words: word A contains the time calibration, and
words B and C contain the setting for the monitor pulses
(see Table 2).
Table 1 Time calibration
CALIBRATION PERIOD
1 minute
2 minutes
CORRECTION PER STEP (n = 1)
ppm
2.03
1.017
seconds per day
0.176
0.088
CORRECTION PER STEP (n = 127)
ppm
258
129
seconds per day
22.3
11.15
Table 2 Words and bits
WORD
A
1
BIT
23456
number of 8192 Hz pulses to be removed
B
lowest stage: duty cycle number of driving stages
highest stage:
duty cycle and
stretching
C
pulse width
maximum time delay between positive
and negative detection pulses
78
calibration
period
factory test bit
EOL factory test
voltage
bit
2003 Dec 17
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부품번호상세설명 및 기능제조사
PCA2001AA

32 kHz watch circuit with programmable adaptive motor pulse

NXP Semiconductors
NXP Semiconductors

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