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PCA5010 데이터시트 PDF




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부품번호 PCA5010 기능
기능 Pager baseband controller
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PCA5010 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCA5010
Pager baseband controller
Product specification
File under Integrated Circuits, IC17
1998 Nov 02




PCA5010 pdf, 반도체, 판매, 대치품
Philips Semiconductors
Pager baseband controller
Product specification
PCA5010
3 GENERAL DESCRIPTION
The PCA5010 pager baseband controller is manufactured
in an advanced CMOS/OTP technology.
The PCA5010 is an 8-bit microcontroller especially suited
for pagers. For this purpose, features such as a
4 or 2 level FSK demodulator, filter, clock recovery,
protocol timer, DC/DC converter optimized for small
paging systems and RTC are integrated on-chip.
The device is optimized for low power consumption.
The PCA5010 has several software selectable modes for
power reduction: Idle and Power-down mode of the
microcontroller and Standby and OFF mode of the DC/DC
converter.
The instruction set of the PCA5010 is based on that of the
80C51. The PCA5010 also functions as an arithmetic
processor having facilities for both binary and BCD
arithmetic plus bit-handling capabilities. The instruction set
consists of over 100 instructions: 49 one-byte, 46 two-byte
and 16 three-byte.
This data sheet details the properties of the PCA5010.
For details on the I2C-bus functions see “The I2C-bus and
how to use it”. For details on the basic 80C51 properties
and features see “Data Handbook IC20”.
1998 Nov 02
4

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PCA5010 전자부품, 판매, 대치품
Philips Semiconductors
Pager baseband controller
Product specification
PCA5010
SYMBOL
P1.4
VSS
VDD
ALE
PSEN
EA
TCLK
VPP
P1.6
P1.7
XTL2
XTL1
VBAT
VDD(DC)
VIND
VSS(DC)
RESETIN
PIN TYPE
DESCRIPTION
29 I/O If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.4 can be used as
general purpose P1 port pin. If the UART function is required, then a logic 1
must be written to P1.4. This I/O then becomes the TXD/clock line of the UART.
P1.4 has external interrupt INT6 (X6) assigned.
30 S ground (connected to substrate)
31 S supply voltage for the core logic and most peripheral drivers of the PCA5010
(see VDDA)
32 I/O Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory.
33 I/O Program Store Enable: The read strobe to external program memory. When
the device is executing code from the external program memory, PSEN is
activated for each code byte fetch.
34 I/O External Access Enable: EA must be externally held LOW to enable the
device to fetch code from external program memory locations 0000H to 7FFFH.
If EA is held HIGH, the device executes from internal program memory unless
the program counter contains an address greater the 7FFFH (32 kbytes).
35 I clock input for use as timing reference in external access mode and emulation
36 S Programming voltage (12.5 V) for the OTP. Is connected to VSS in the
application.
37 I/O If the I2C-bus is disabled (ENS1 in S1CON.6 = 0) then P1.6 can be used as
general purpose P1 port pin. If the I2C-bus function is required, then a logic 1
must be written to P1.6. This I/O then becomes the clock line of the I2C-bus.
P1.6 is equipped with an open-drain output buffer. The pin has no clamp diode
to VDD.
38 I/O If the I2C-bus is disabled (ENS1 in S1CON.6 = 0) then P1.7 can be used as
general purpose P1 port pin. If the I2C-bus function is required, then a logic 1
must be written to P1.7. This I/O then becomes the data line of the I2C-bus.
P1.7 is equipped with an open-drain output buffer. The pin has no clamp diode
to VDD.
39 O output from the current source oscillator amplifier
40 I input to the inverting oscillator amplifier and time reference for pager decoder,
real-time clock and timers
41 S Supply terminal from battery. Is used for supplying parts of the chip that need to
operate at all times.
42 O Supply voltage output of the DC/DC converter. An external capacitor is
required.
43 I Current input for the DC/DC converter. The booster inductor needs to be
connected externally.
44 S ground (connected to substrate) OTP
45 I Schmitt trigger reset input for the PCA5010. External R and C need to be
connected to the battery supply. All internal storage elements (except
microcontroller RAM) are initialized when this input is activated.
1998 Nov 02
7

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