Datasheet.kr   

PCA8515 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 PCA8515
기능 Stand-alone OSD
제조업체 NXP
로고 NXP 로고 



전체 30 페이지

		

No Preview Available !

PCA8515 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCA8515
Stand-alone OSD
Preliminary specification
File under Integrated Circuits, IC14
Philips Semiconductors
1995 Jan 19




PCA8515 pdf, 반도체, 판매, 대치품
VDD
VSS
RESET
SCL/SCLK
SDA/SIN
E
HIO/ I2 C
C
HSYNC
VSYNC
EXTERNAL/INTERNAL
DATA SWITCHING
BUFFER
I 2 C SLAVE
RECEIVER OR
HIGH-SPEED I/O
RECEIVER
CHARACTER SIZE
REGISTER/
CONTROL
HORIZONTAL
POSITION
REGISTER/
COUNTER
WRITE ADDRESS
COUNTER
ADDRESS
BUFFER
SELECTOR
DISPLAY
CHARACTER
RAM
VERTICAL
POSITION
REGISTER/
COUNTER
DISPLAY
ROM
CONTROL
REGISTER
I/O
PORT
BUFFERS
INSTRUCTION
DECODER
PLL
OSCILLATOR
VSYNC
HSYNC
CSYNC
SEPARATION
INTERNAL
SYNCHRONOUS
CIRCUIT
CRYSTAL
OSCILLATOR
CONTROL
SIGNALS
TESTING
CIRCUITRY
DISPLAY CONTROL
AND OUTPUT STAGE
ACM(VOB2)
3 P00
P01
P04/ACM (VOB2)
AV DD
AV SS
XTAL1(IN)
XTAL2(OUT)
TEST1
12
R(VOW0)
FB(VOB)
TEST2 TI00 to TI11 G(VOW1) I(VOW3)
B(VOW2)
MLC347
Fig.1 Block diagram.

4페이지










PCA8515 전자부품, 판매, 대치품
Philips Semiconductors
Stand-alone OSD
Preliminary specification
PCA8515
6 SERIAL I/O
The PCA8515 has two means by which it can
communicate with a microcontroller: a fast I2C-bus serial
interface and a High-speed serial interface. Selection of
either interface is achieved via pin 15, HIO/I2C. When
HIO/I2C is LOW, the HIO serial interface is selected. When
HIO/I2C is HIGH, the I2C-bus serial interface is selected.
The PCA8515 is programmed by a series of commands
sent via one of these interfaces. There are 16 commands;
each command selecting different functions of the
PCA8515. The 16 commands are described in detail in
Chapter 9.
6.1 I2C-bus serial interface
The I2C-bus serial interface is selected by driving pin 15
(HIO/I2C) HIGH. Data transmission conforms to the fast
I2C-bus protocol; the maximum transmission rate being
400 kHz. The PCA8515 operates in the slave receiver
mode and therefore in normal operation is ‘write only’ from
the master device.
The format of the data streams sent via the I2C-bus
interface is shown in Fig.3. The first data byte is the slave
address 1011 101Xb. The last bit of the slave address is
always a logic 0, except in the Test mode when it could be
a logic 1. Subsequent data bytes contain the commands
for control of the device. Upon the successful reception of
a complete data byte by the shift register, an Acknowledge
bit is sent. A STOP condition terminates the data transfer
operation.
The I2C-bus interface is reset to its initial state (waiting for
a slave address call) by the following conditions:
After a master reset
After a bus error has been detected on the I2C-bus
interface.
Under both these conditions the data held in the shift
register is abandoned.
6.1.1 MAXIMUM SPEED OF THE I2C-BUS
The maximum I2C-bus transmission rate that the
PCE8515 can receive is 400 kHz. However, if the data
byte being transmitted is for display RAM then internal
synchronization of the write operation from the shift
register to the display RAM location is necessary. This will
reduce the maximum transmission speed.
The synchronization process is carried out by on-chip
hardware and takes place during the HSYNC retrace
period when VSYNC is inactive. The I2C-bus clock is
pulled LOW if a complete display RAM data byte is
received before HSYNC becomes active. The I2C-bus
clock will be released when HSYNC becomes active and
then the contents of the shift register will be written into the
display RAM location.
6.2 High-speed serial interface (HIO)
The High-speed serial interface is selected when pin 15
(HIO/I2C) is pulled LOW. The High-speed serial interface
has a 3-wire communication protocol; the maximum
transmission rate being 1 MHz. The interface protocol is
illustrated in Fig.4 and described below:
1. Pin 14 (E) the chip enable pin is driven HIGH. This
LOW-to-HIGH transition clears the shift register and
resets the serial input circuit.
2. On the first HIGH-to-LOW transition of SCLK after the
interface has been enabled, the first data bit (D0) must
be present at the SIN pin.
3. On the following LOW-to-HIGH transition of SCLK, the
first data bit (D0) will be latched into the shift register.
4. On the next HIGH-to-LOW transition of SCLK the
second data bit (D1) must be present at the SIN pin.
Data bit (D1) will be latched into the shift register on
the following LOW-to-HIGH transition of SCLK.
5. The operation specified in step 4 above is repeated
another 6 times, thus loading the shift register with a
complete data byte. This data byte is then transferred
to the command interpreter which takes the
appropriate action.
6. Providing the chip enable signal remains HIGH, a 2nd
data byte can be transferred. The 1st data bit of the
next data transfer takes place on the falling edge of the
SCLK signal.
The following points should be noted:
If the chip enable signal is pulled LOW at any time the
shift operation in progress is stopped and the HIO slave
receiver is disabled
The rising edge of the chip enable signal resets the HIO
slave receiver.
1995 Jan 19
7

7페이지



구       성총 30 페이지
다운로드[ PCA8515.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
PCA85132

LCD driver for low multiplex rates

NXP
NXP
PCA8514

Stand-alone OSD

NXP
NXP

DataSheet.kr    |   2019   |  연락처   |  링크모음   |   검색  |   사이트맵