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PCA9500BS 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PCA9500BS은 전자 산업 및 응용 분야에서
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부품번호 PCA9500BS 기능
기능 8-bit I2C and SMBus I/O port with 2-kbit EEPROM
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PCA9500BS 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PCA9500
8-bit I2C and SMBus I/O port with
2-kbit EEPROM
Product data
Supersedes data of 27 Sep 2002
2003 Jun 27
Philips
Semiconductors




PCA9500BS pdf, 반도체, 판매, 대치품
Philips Semiconductors
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
Product data
PCA9500
FUNCTIONAL DESCRIPTION
WRITE PULSE
DATA FROM
SHIFT REGISTER
POWER-ON
RESET
READ PULSE
DATA TO
SHIFT REGISTER
DQ
FF
CI
S
DQ
FF
CI
S
100 µA
Figure 4. Simplified schematic diagram of each I/O
VDD
I/O0 TO I/O7
VSS
SW00546
DEVICE ADDRESSING
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in
Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.
SLAVE ADDRESS
SLAVE ADDRESS
0 1 0 0 A2 A1 A0 R/W
1 0 1 0 A2 A1 A0 R/W
(a) I/O EXPANDER
(b) MEMORY
FIXED
HARDWARE
PROGRAMMABLE
a.
FIXED
Figure 5. PCA9500 slave addresses
HARDWARE
PROGRAMMABLE
b.
SW01075
The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write
operation.
CONTROL REGISTER
The PCA9500 contains a single 8-bit register called the Control Register, which can be written and read via the I2C-bus. This register is sent
after a successful acknowledgment of the slave address.
It contains the I/O operation information.
I/O OPERATIONS (see also Figure 4)
Each of the PCA9500s eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE
mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7).
2003 Jun 27
4

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PCA9500BS 전자부품, 판매, 대치품
Philips Semiconductors
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
Product data
PCA9500
MEMORY OPERATIONS
Write operations
Write operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long, providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.
Write operation is possible when WC control pin put at a low logic
level (0). When this control signal is set at 1, write operation is not
possible and data in the memory is protected.
Byte Write and Page Write explained below assume that Write
Control pin (WC) is set to 0.
Byte Write (see Figure 9)
To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PCA9500 will respond
with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the
data. The PCA9500 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non-volatile memory. Only write and read operations to the
Quasi-bidirectional I/O are allowed during the internal write cycle.
Page Write (see Figure 10)
A page write is initiated in the same way as the byte write. If after
sending the first word of data, the stop condition is not received the
PCA9500 considers subsequent words as data. After each data
word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should
the master not send a stop condition after four data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA
SDA S 1 0 1 0 A2 A1 A0 0 A
A DATA
AP
START CONDITION
R/W ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
Figure 9. Byte write
ACKNOWLEDGE
FROM SLAVE
STOP CONDITION.
WRITE TO THE
MEMORY IS
PERFORMED
SW02036
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
SDA S 1 0 1 0 A2 A1 A0 0 A
START CONDITION
R/W ACKNOWLEDGE
FROM SLAVE
DATA TO MEMORY
A
DATA n
A
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
Figure 10. Page Write
DATA TO MEMORY
DATA n + 3
AP
STOP CONDITION.
WRITE TO THE MEMORY
IS PERFORMED
SW02037
2003 Jun 27
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PCA9500BS

8-bit I2C and SMBus I/O port with 2-kbit EEPROM

NXP Semiconductors
NXP Semiconductors

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