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PCA9510 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PCA9510은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 PCA9510 기능
기능 Hot swappable I2C and SMBus bus buffer
제조업체 NXP Semiconductors
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PCA9510 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PCA9510; PCA9511
Hot swappable I2C and SMBus bus buffer
Product data sheet
Supersedes data of 2003 Dec 18
2004 Oct 05
Philips
Semiconductors




PCA9510 pdf, 반도체, 판매, 대치품
Philips Semiconductors
Hot swappable I2C and SMBus bus buffer
Product data sheet
PCA9510; PCA9511
TYPICAL APPLICATION — PCA9510
VCC
(2.7 V to
5.5 V)
R1
10 k
SCLIN
R2
10 k8
3
C1
0.01 µF R5
10 k
R3
10 k
2
R4
10 k
SDAIN
67
ENABLE
BLOCK DIAGRAM — PCA9510
1
ENABLE
5
READY
GND
4
Figure 2. Typical application — PCA9510
SDAIN 6
CONNECT
100 k
RCH1
100 k
RCH2
BACKPLANE-TO-CARD
CONNECTION
CONNECT
ENABLE
1 VOLT
PRECHARGE
CONNECT
SCLOUT
SDAOUT
SW02149
8 VCC
7 SDAOUT
SCLIN 3
CONNECT
0.55VCC/
0.45VCC
UVLO
ENABLE 1
130 µs
DELAY
2004 Oct 05
BACKPLANE-TO-CARD
CONNECTION
CONNECT
2 SCLOUT
0.55VCC/
0.45VCC
STOP BIT AND
BUS IDLE
0.5 µA
20 pF
UVLO
0.5 pF
Figure 3. Block diagram — PCA9510
CONNECT
RD
QB
S
5 READY
4 GND
CONNECT
SW02150
4

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PCA9510 전자부품, 판매, 대치품
Philips Semiconductors
Hot swappable I2C and SMBus bus buffer
Product data sheet
PCA9510; PCA9511
Propagation Delays
The delay for a rising edge is determined by the combined pull-up
current from the bus resistors and the rise time accelerator current
source and the effective capacitance on the lines. If the pull-up
currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides.
The tPLH may be negative if the output capacitance is less than the
input capacitance and would be positive if the output capacitance is
larger than the input capacitance, when the currents are the same.
The tPHL can never be negative because the output does not start to
fall until the input is below 0.7VCC, and the output turn on has a non
zero delay, and the output has a limited maximum slew rate, and
even if the input slew rate is slow enough that the output catches up
it will still lag the falling voltage of the input by the offset voltage. The
maximum tPHL occurs when the input is driven low with zero delay
and the output is still limited by its turn on delay and the falling edge
slew rate. The output falling edge slew rate is a function of the
internal maximum slew rate which is a function of temperature. VCC
and process, as well as the load current and the load capacitance.
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on
to quickly slew the SDA and SCL lines high once the input level of
0.6 V for the PCA9511 is exceeded. The rising edge rate should be
at least 1.25 V/µs to guarantee turn on of the accelerators. The
PCA9510 doesn’t have any rise time accelerator circuitry.
READY Digital Output
This pin provides a digital flag which is low when either ENABLE is
low or the start-up sequence described earlier in this section has not
been completed. READY goes high when ENABLE is high and
start-up is complete. The pin is driven by an open drain pull-down
capable of sinking 3 mA while holding 0.4 V on the pin. Connect a
resistor of 10 k to VCC to provide the pull-up.
ENABLE Low Current Disable
Grounding the ENABLE pin disconnects the backplane side from the
card side, disables the rise-time accelerators, drives READY low,
disables the bus precharge circuitry, and puts the part in a low
current state. When the pin voltage is driven all the way to VCC, the
part waits for data transactions on both the backplane and card
sides to be complete before reconnecting the two sides.
Resistor Pull-up Value Selection
The system pull-up resistors must be strong enough to provide a
positive slew rate of 1.25 V/µs on the SDA and SCL pins, in order to
activate the boost pull-up currents during rising edges. Choose
maximum resistor value using the formula:
R v 800 @ 103
VCC(MIN) * 0.6
C
where R is the pull-up resistor value in , VCC(MIN) is the
minimum VCC voltage in volts and C is the equivalent bus
capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always choose R
16 kfor VCC = 5.5 V maximum, R 24 kfor VCC = 3.6 V
maximum. The start-up circuitry requires logic high voltages on
SDAOUT and SCLOUT to connect the backplane to the card, and
these pull-up values are needed to overcome the precharge voltage.
See the curves in Figures 7 and 8 for guidance in resistor pull-up
selection.
RPULLUP
(k)
30
25
20
RMAX = 24 k
15
RISE-TIME > 300 ns
21
RECOMMENDED
PULL-UP
5
0
0 100
200 300
400
CBUS (pF)
SW02115
Figure 7. Bus requirements for 3.3 V systems
20
RPULLUP
(k)
15
21
5
RMAX = 16 k
RISE-TIME
> 300 ns
RECOMMENDED
PULL-UP
0
0 100
200 300
400
CBUS (pF)
SW02116
Figure 8. Bus requirements for 5 V systems
Minimum SDA and SCL Capacitance Requirements
The device connection circuitry requires a minimum capacitance
loading on the SDA and SCL pins in order to function properly. The
value of this capacitance is a function of VCC and the bus pull-up
resistance. Estimate the bus capacitance on both the backplane and
the card data and clock buses, and refer to Figures 7 and 8 to
choose appropriate pull-up resistor values. Note from the figures
that 5 V systems should have at least 47 pF capacitance on their
buses and 3.3 V systems should have at least 22 pF capacitance for
proper operation. Although the device has been designed to be
marginally stable with smaller capacitance loads, for applications
with less capacitance, provisions need to be made to add a
capacitor to ground to ensure these minimum capacitance
conditions if oscillations are noticed during initial signal integrity
verification.
2004 Oct 05
7

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