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PDF BTS7810K Data sheet ( Hoja de datos )

Número de pieza BTS7810K
Descripción TrilithIC
Fabricantes Infineon Technologies AG 
Logotipo Infineon Technologies AG Logotipo



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TrilithIC
BTS 7810 K
Data Sheet
1 Overview
1.1 Features
• Quad D-MOS switch
• Free configurable as bridge or quad-switch
• Optimized for DC motor management applications
• Low RDS ON: 26 mhigh-side switch, 14 mlow-side
switch (typical values @ 25 °C)
• Maximum peak current: typ. 42 A @ 25 °C=
• Very low quiescent current: typ. 4 µA @ 25 °C=
• Small outline, thermal optimized PowerPak
• Load and GND-short-circuit-protection
• Operates up to 40 V
• Status flag for over temperature
• Open load detection in Off-mode
• Overtemperature shut down with hysteresis
• Internal clamp diodes
• Isolated sources for external current sensing
• Under-voltage detection with hysteresis
P-TO263-15-1
Type
BTS 7810 K
Ordering Code
Q67060-S6129
Package
P-TO263-15-1
1.2 Description
The BTS 7810 K is part of the TrilithIC family containing three dies in one package:
One double high-side switch and two low-side switches. The drains of these three
vertical DMOS chips are mounted on separated leadframes. The sources are connected
to individual pins, so the BTS 7810 K can be used in H-bridge- as well as in any other
configuration. The double high-side is manufactured in SMART SIPMOS® technology
which combines low RDS ON vertical DMOS power stages with CMOS control circuit. The
high-side switch is fully protected and contains the control and diagnosis circuit. To
achieve low RDS ON and fast switching performance, the low-side switches are
manufactured in S-FET 2 logic level technology. The equivalent standard product is the
SPD30N06S2L-13.
Data Sheet 1 2003-03-11

1 page




BTS7810K pdf
BTS 7810 K
1.6 Circuit Description
Input Circuit
The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with
hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into
the necessary form for driving the power output stages. The inputs are protected by ESD
clamp-diodes.
The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical
power-MOS-FETs.
Output Stages
The output stages consist of a low RDS ON Power-MOS H-bridge. In H-bridge
configuration, the D-MOS body diodes can be used for freewheeling when commutating
inductive loads. If the high-side switches are used as single switches, positive and
negative voltage spikes which occur when driving inductive loads are limited by
integrated power clamp diodes.
Short Circuit Protection
The outputs are protected against
– output short circuit to ground
– overload (load short circuit).
An internal OP-amp controls the Drain-Source-voltage by comparing the DS-voltage-
drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the
output current depending on the junction temperature and the drop voltage.
In the case of overloaded high-side switches the status output is set to low.
Overtemperature Protection
The high-side switches incorporate an overtemperature protection circuit with hysteresis
which switches off the output transistors and sets the status output to low.
Undervoltage-Lockout (UVLO)
When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis.
The high-side output transistors are switched off if the supply voltage VS drops below the
switch off value VUVOFF.
Open Load Detection
Open load is detected by voltage measurement in off state. If the output voltage exceeds
a specified level the error flag is set with a delay.
Data Sheet 5 2003-03-11

5 Page





BTS7810K arduino
BTS 7810 K
3.3 Electrical Characteristics (cont’d)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symb
Limit Values Unit Test Condition
ol min. typ. max.
Thermal Shutdown
Thermal shutdown
junction temperature
Thermal switch-on
junction temperature
Temperature hysteresis
Tj SD
Tj SO
T
155 180 190 °C –
150 170 180 °C –
– 10 – °C T = TjSD TjSO
Status Flag Output ST of highside switch
Low output voltage
VST L
0.2 0.6 V IST = 1.6 mA
Leakage current
IST LK
5
µA VST = 5 V
Zener-limit-voltage
VST Z
5.4
– V IST = 1.6 mA
Status change after
t d(SToffo+) – 20 µs
positive input slope with
open load
Status change after
t d(SToffo-) – 700 µs
negative input slope with
open load
Status change after
positive input slope with
overtemperature
t d(STofft+)
1.6 10 µs RST = 47 k
Status change after
negative input slope with
overtemperature
td(STofft-)
14 100 µs RST = 47 k
Note: times are not subject to production test - specified by design
Open load detection in Off condition
Open load detection
voltage
V 2OUT(OL) 3 4 V
Data Sheet 11 2003-03-11

11 Page







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