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부품번호 PCA9518D 기능
기능 Expandable 5-channel I2C hub
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PCA9518D 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PCA9518
Expandable 5-channel I2C hub
Product data sheet
Supersedes data of 2004 Jun 24
2004 Sep 29
Philips
Semiconductors




PCA9518D pdf, 반도체, 판매, 대치품
Philips Semiconductors
Expandable 5-channel I2C hub
Product data sheet
PCA9518
FUNCTIONAL DESCRIPTION
The PCA9518 BiCMOS integrated circuit is a five way hub repeater,
which enables I2C and similar bus systems to be expanded in
increments of five with only one repeater delay and no functional
degradation of system performance.
The PCA9518 BiCMOS integrated circuit contains five
multi-directional, open drain buffers specifically designed to support
the standard low-level-contention arbitration of the I2C-bus. Except
during arbitration or clock stretching, the PCA9518 acts like a pair of
non-inverting, open drain buffers, one for SDA and one for SCL.
Enable
The enable pins EN1 through EN4 are active-HIGH and have
internal pull-up resistors. Each enable pin ENn controls its
associated SDAn and SCLn ports. When LOW, the ENn pin blocks
the inputs from SDAn and SCLn, as well as disabling the output
drivers on the SDAn and SCLn pins. The enable pins should only
change state when both the global bus and the local port are in an
idle state to prevent system failures.
The active-HIGH enable pins allow the use of open drain drivers
which can be wire-ORed to create a distributed enable where either
centralized control signal (master) or spoke signal (submaster) can
enable the channel when it is idle.
Expansion
The PCA9518 includes 4 open drain I/O pins used for expansion.
Two expansion pins, EXPSDA1 and EXPSDA2 are used to
communicate the internal state of the serial data within each hub to
the other hubs. The EXPSDA1 pins of all hubs are connected
together to form an open-drain bus. Similarly, all EXPSDA2 pins,
EXPSCL1 pins, and all EXPSCL2 pins are connected together
forming a 4-wire bus between hubs.
When it is necessary to be able to deselect every port, each
expansion device only contributes 4 ports which can be enabled or
disables because the fifth does not have an enable pin.
Pull-up resistors are required on the EXPXXXX3 pins even if only
one PCA9518 is used.
I2C Systems
As with the standard I2C system, pull-up resistors are required to
provide the logic HIGH levels on the Buffered bus. (Standard
open-collector or open-drain configuration of the I2C-bus). The size
of these pull-up resistors depends on the system, but each side of
the repeater must have a pull-up resistor. This part is designed to
work with standard mode (0 to 100 kHz) and fast mode (0 to
400 kHz) I2C devices in addition to SMBus devices. Standard mode
I2C devices only specify 3 mA output drive, this limits the termination
current to 3 mA in a generic I2C system where standard mode
devices and multiple masters are possible. Please see Application
Note AN255 “I2C & SMBus Repeaters, Hubs and Expanders” for
additional information on sizing resistors.
APPLICATION INFORMATION
A typical application is shown in Figure 4. In this example, the
system master is running on a 3.3 V I2C-bus while the slaves are
connected to a 3.3 V or 5 V bus. All buses run at 100 kHz unless
slave 3, 4 and 5 are isolated from the bus. Then the master bus and
slave 1, 2 and 6 can run at 400 kHz.
Any segment of the hub can talk to any other segment of the hub.
Bus masters and slaves can be located on any segment with 400 pF
load allowed on each segment.
The PCA9518 is 5 V tolerant so it does not require any additional
circuitry to translate between the different bus voltages.
When one port of the PCA9518 is pulled LOW by a device on the
I2C-bus, a CMOS hysteresis type input detects the falling edge and
drives the EXPXXX1 line LOW, when the EXPXXX1 voltage is less
than1/2VCC, the other ports are pulled down to the VOL of the
PCA9518 which is typically 0.5 V.
In order to illustrate what would be seen in a typical application, refer
to Figure 5. If the bus master in Figure 4 were to write to the slave
through the PCA9518, we would see the waveform shown in Figure
5. This looks like a normal I2C transmission except for the small foot
preceding each clock LOW to HIGH transition and proceeding each
data LOW to HIGH transition for the master. The foot height is the
difference between the LOW level driven by the master and the
higher voltage LOW level driven by the PCA9518 repeater. Its width
corresponds to an effective clock stretching coming from the
PCA9518 which delays the rising edge of the clock. That same
magnitude of delay is seen on the rising edge of the data. The foot
on the rising edge of the data is extended through the 9th clock
pulse as the PCA9518 repeats the acknowledge from the slave to
the master. The clock of the slave looks normal except the VOL is
the 0.5 V level generated by the PCA9518. The SDA at the slave
has a particularly interesting shape during the 9th clock cycle where
the slave pulls the line below the value driven by the PCA9518
during the acknowledge and then returns to the PCA9518 level
creating a foot before it completes the LOW to HIGH transition. SDA
lines other than the one with the master and the one with the slave
have a uniform LOW level driven by the PCA9518 repeater.
The other four waveforms are the expansion bus signals and are
included primarily for timing reference points. All timing on the
expansion bus is with respect to 0.5 VCC. EXPSDA1 is the
expansion bus that is driven LOW whenever any SDA pin falls
below 0.3 VCC. EXPSDA2 is the expansion bus that is driven LOW
whenever any pin is 0.4 V. EXPSCL1 is the expansion bus that is
driven LOW whenever any SCL pin falls below 0.3 VCC. EXPSCL2
is the expansion bus that is driven LOW whenever any SCL pin is
0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the
last one being held below 0.4 V by an external driver starts to rise.
The last SDA to rise above 0.4 V is held down by the PCA 9518 to
0.5 V until after the delay of the circuit which determines that it was
the last to rise, then it is allowed to rise above the 0.5 V level driven
by the PCA9518. Considering the bus 0 SDA to be the last one to go
above 0.4 V, then the EXPSDA1 returns to HIGH after the
EXPSDA2 is HIGH and either the bus 0 SDA rise time is 1 µs or,
when the bus 0 SDA reaches 0.7 VCC, whichever occurs first. After
both EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines
are allowed to rise. The same description applies for the EXPSCL1,
EXPSCL2, and SCL pins.
3. XXXX is SDA1, SDA2, SCL1, or SCL2
XXX is SDA or SCL
2004 Sep 29
4

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PCA9518D 전자부품, 판매, 대치품
Philips Semiconductors
Expandable 5-channel I2C hub
Product data sheet
PCA9518
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND.
SYMBOL
VCC to GND
Vbus
I
Ptot
Tstg
Tamb
PARAMETER
Supply voltage range VCC
Voltage range I2C-bus, SCL or SDA
DC current (any pin)
Power dissipation
Storage temperature range
Operating ambient temperature range
LIMITS
MIN.
MAX.
–0.5 +7
–0.5 +7
— 50
— 300
–55 +125
–40 +85
UNIT
V
V
mA
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 3.6 V; GND = 0 V; Tamb = –40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
LIMITS
TYP.
MAX.
UNIT
Supplies
VCC
ICCH
ICCL
DC supply voltage
Quiescent supply current,
both channels HIGH
Quiescent supply current,
both channels LOW
VCC = 3.6 V;
SDAn = SCLn = VCC
VCC = 3.6 V;
one SDA and one SCL = GND,
other SDA and SCL open
3.0 3.3
— 7.5
—9
3.6 V
10 mA
11 mA
ICCLc
Quiescent supply current in contention
VCC = 3.6 V;
SDAn = SCLn = GND
—9
11 mA
Input SCL; input/output SDA
VIH HIGH-level input voltage, SCL, SDA
VIL LOW-level input voltage, SCL, SDA
(Note 1)
0.7 VCC
–0.5
5.5
0.3 VCC
V
V
VILc LOW-level input voltage contention,
SCL, SDA (Note 1)
–0.5 — 0.4 V
VIK
II
IIL
VOL
VOL–VILc
Input clamp voltage
Input leakage current
Input current LOW, SDA, SCL
LOW level output, SCL, SDA
LOW level input voltage below
output LOW level voltage
II = –18 mA
VI = 3.6 V
VI = 0.2 V, SDA, SCL
IOL = 02 or 6 mA
Guaranteed by design
— — –1.2 V
——
±1 µA
——
5 µA
0.47 0.52
0.6
V
——
70 mV
CI Input capacitance
Enable 1–4
VI = 3 V or 0 V
—6
8 pF
VIL LOW level input voltage
VIH HIGH level input voltage
IIL Input current LOW
ILI Input leakage current
CI Input capacitance
Expansion Pins
VI = 0.2 V, EN1–EN4
VI = 3.0 V or 0 V
–0.5 —
2.0 —
— 10
–1 —
—3
0.8 V
5.5 V
30 µA
1 µA
7 pF
VIH HIGH level input voltage, EXP*
0.55
VCC
5.5
V
VIL LOW level input voltage, EXP*
–0.5
— 0.45 VCC V
IIL Input current LOW, EXP*
VI = 0.2 V, EXP*
——
5 µA
VOL LOW level output, EXP*
IOL = 12 mA
— — 0.5 V
CI Input capacitance
VI = 3.0 V or 0 V
—6
8 pF
NOTE:
1. VIL specification is for the first LOW level seen by the SDAx/SCLx lines. VILc is for the second and subsequent LOW levels seen by the
SDAx/SCLx lines.
2. Test performed with IOL = 10 µA.
2004 Sep 29
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