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PDF BU207 Data sheet ( Hoja de datos )

Número de pieza BU207
Descripción POWER TRANSISTORS(5.0A/1300-1500V/55W)
Fabricantes Mospec Semiconductor 
Logotipo Mospec Semiconductor Logotipo



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No Preview Available ! BU207 Hoja de datos, Descripción, Manual

Standard ICs
8-bit serial in, parallel out driver IC
BU2050F
The BU2050F is a driver IC that is comprised of an 8-bit shift register and a latch (serial in / parallel out). The data
read into the shift register can be asynchronously latched. The CMOS outputs can provide 25mA (Max.) of current
per output, making this IC ideal for a wide range of applications including driving LEDS.
Applications
Printers, mini-component stereo systems, car audio systems, and musical instruments
Features
1) Regardless of the clock and data input, the CLR pin
resets the latch circuit, and sets all outputs to the low
level.
2) Output drive capacity: 25mA / output (Max.).
3) Input pin hysteresis: 0.5V (Typ.).
Block diagram
VDD P2
14 13
P1 CLR STB CLK DATA
12 11 10
9
8
CTRL
SHIFT REGISTER
LATCH
OUTPUT Driver
1234567
P3 P4 P5 VSS P6 P7 P8
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BU207 pdf
Standard ICs
Timing chart
CLK
CLR
STB
DATA
P1
P2
P3
P4
P5
P6
P7
P8
BU2050F
Circuit operation
This IC is made up of an 8-bit shift register, a latch, and
an output driver.
The four input pins (data (DATA), strobe (STB), latch
reset (CLR), and ckock (CLK)) are all hysteresis inputs
(0.5V Typ.).
The reset function applies to all bits in the latch circuit.
When CLR is low, the latch circuit is reset asynchro-
nously, regardless of the other inputs, and all outputs
are set to low. The CLR pin is normally high.
The serial data input to the data pin is synchronously
read into the shift register on the rising edge of the
clock.
When STB is low (CLR is high), the data in the shift
register is transferred to the latch circuit, and output on
the parallel data output pins (P1 ~ P8).
When STB is high, the latch circuit and output data
does not change.
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