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PDF BU2114F Data sheet ( Hoja de datos )

Número de pieza BU2114F
Descripción 8-bit shift register and latch driver
Fabricantes ROHM Semiconductor 
Logotipo ROHM Semiconductor Logotipo



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No Preview Available ! BU2114F Hoja de datos, Descripción, Manual

Standard ICs
8-bit shift register and latch driver
BU2114 / BU2114F
The BU2114 and BU2114F are CMOS ICs with low power consumption, and are equipped with an 8-bit shift register
latch. Data in the shift register can be latched asynchronously. The outputs (O1 to O8) are open drain outputs
(because there is no protection diode, a maximum voltage above VDD, of up to 7V, can be applied), and one output
can drive 36 mA. A total output of up to 150 mA can be driven (when using static operation).
Applications
These are designed for a wide range of applications in microcomputer peripheral circuits, such as in industrial equip-
ment, office telephones, audio visual equipment, and expansion input and output boards.
Features
1) The CMOS configuration enables low power con-
sumption.
2) Open drain output.
3) Latch to 8-bit shift register provided, enabling drive
of up to 150mA. (ISINK = 36mA)
4) Cascade connections possible.
Absolute maximum ratings (unless otherwise noted, Ta = 25°C)
Parameter
Symbol
Limits
Applied voltage
Input voltage
Operating temperature
VDD
VIN
Topr
– 0.3 ~ + 7.0
– 0.3 ~ VDD0.3
– 25 ~ + 75
Storage temperature
Tstg – 55 ~ + 150
Input protection diode current
BU2114
Power dissipation
BU2114F
ID
Pd
± 20
11001
4002
1 Power dissipation is reduced by 8.8mW for each increase in Ta of 1°C over 25°C.
2 Power dissipation is reduced by 3.2mW for each increase in Ta of 1°C over 25°C.
Unit
V
V
°C
°C
mA
mW
Recommended operating conditions (unless otherwise noted, Ta = 25°C)
Parameter
Symbol Min. Typ. Max.
Unit
Recommend voltage
VDD 4.5 5.0 5.5
V
Input voltage
VIN 0 — VDD V
Output voltage
VOUT 0 — VDD
V
Not designed for radiation resistance.
Conditions
SIN, CK, LATCH, EN, RST
SOUT
1

1 page




BU2114F pdf
Standard ICs
BU2114 / BU2114F
Timing characteristics (unless otherwise noted, Ta = 25°C, VDD = 5.0V)
Parameter
Symbol
Conditions
Min. Typ.
Clock frequency
f Input duty 50%
Clock pulse width
tcw — 100 —
Latch pulse width
Data setup time
Data hold time
Clock latch time
trw — 100 —
tsu
CKSIN
100 —
th
CKSIN
100 —
tdtl — 100 —
Max.
5
Unit
MHz
ns
ns
ns
ns
ns
SIN
CK
LATCH
2.5V
2.5V
tsu th
tcw
tdtl
trw
Fig.2 Timing conditions
5

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