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PCA9533DP 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PCA9533DP은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 PCA9533DP 기능
기능 4-bit I2C LED dimmer
제조업체 NXP Semiconductors
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PCA9533DP 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PCA9533
4-bit I2C LED dimmer
Product data sheet
Supersedes data of 2003 Sep 19
Philips
Semiconductors
2004 Oct 01




PCA9533DP pdf, 반도체, 판매, 대치품
Philips Semiconductors
4-bit I2C LED dimmer
Product data sheet
PCA9533
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9533/01
is shown in Figure 3 and PCA9533/02 in Figure 4.
SLAVE ADDRESS
1 1 0 0 0 1 0 R/W
SW01037
Figure 3. Slave address — PCA9533/01
SLAVE ADDRESS
1 1 0 0 0 1 1 R/W
SW01038
Figure 4. Slave address — PCA9533/02
The last bit of the address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9533 which will be stored
in the Control Register.
0 0 0 AI 0 B2 B1 B0
RESET STATE: 00h
REGISTER ADDRESS
AUTO-INCREMENT FLAG
Figure 5. Control register
SW01034
The lowest 3 bits are used as a pointer to determine which register
will be accessed.
If the auto-increment flag is set, the three low order bits of the
Control Register are automatically incremented after a read or write.
This allows the user to program the registers sequentially. The
contents of these bits will rollover to ‘000’ after the last register is
accessed.
When auto-increment flag is set (AI = 1) and a read sequence is
initiated, the sequence must start by reading a register different from
the input register (B2 B1 B0 0 0 0 0).
Only the 3 least significant bits are affected by the AI flag.
Unused bits must be programmed with zeroes.
CONTROL REGISTER DEFINITION
B2
B1
B0
REGISTER
NAME
TYPE
000
INPUT
READ
001
010
011
100
101
PSC0
PWM0
PSC1
PWM1
LS0
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
REGISTER
FUNCTION
INPUT
REGISTER
FREQUENCY
PRESCALER 0
PWM
REGISTER 0
FREQUENCY
PRESCALER 1
PWM
REGISTER 1
LED SELECTOR
REGISTER DESCRIPTION
INPUT — INPUT REGISTER
bit 7 6 5
Default 0 0 0
LED LED LED LED
3210
43210
0XXXX
The INPUT register reflects the state of the device pins. Writes to
this register will be acknowledged but will have no effect.
NOTE: The default value “X” is determined by the externally applied
logic level, normally ‘1’ when used for directly driving LED with
pull-up to VDD.
PSC0 — FREQUENCY PRESCALER 0
bit 7 6 5 4 3 2 1 0
default 0 0 0 0 0 0 0 0
PSC0 is used to program the period of the PWM output.
The
period
of
BLINK0
+
(PSC0 )
152
1)
PWM0 — PWM REGISTER 0
bit 7 6 5 4 3 2 1
default 1 0 0 0 0 0 0
0
0
The PWM0 register determines the duty cycle of BLINK0. The
outputs are LOW (LED on) when the count is less than the value in
PWM0 and HIGH (LED off) when it is greater. If PWM0 is
programmed with 00h, then the PWM0 output is always HIGH
(LED off) .
The duty cycle of BLINK0 is:
PWM0
256
PSC1 — FREQUENCY PRESCALER 1
bit 7 6 5 4 3 2 1 0
default 0 0 0 0 0 0 0 0
PSC1 is used to program the period of PWM output.
The
period
of
BLINK1
+
(PSC1 )
152
1)
2004 Oct 01
4

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PCA9533DP 전자부품, 판매, 대치품
Philips Semiconductors
4-bit I2C LED dimmer
Product data sheet
PCA9533
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
S
not acknowledge
acknowledge
12
8
START condition
Figure 9. Acknowledgement on the I2C-bus
9
clock pulse for
acknowledgement
SW00368
2004 Oct 01
7

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