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Número de pieza | PCA9534 | |
Descripción | 8-bit I2C and SMBus/ low power I/O port with interrupt | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PCA9534 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
No Preview Available ! INTEGRATED CIRCUITS
PCA9534
8-bit I2C and SMBus, low power I/O port
with interrupt
Product data sheet
Supersedes data of 2003 Dec 02
2004 Sep 30
Philips
Semiconductors
1 page Philips Semiconductors
8-bit I2C and SMBus low power I/O port with interrupt
Product data sheet
PCA9534
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
WRITE PULSE
CONFIGURATION
REGISTER
DQ
FF
CK Q
DQ
FF
CK Q
OUTPUT
PORT
REGISTER
READ PULSE
Q1
INPUT PORT
REGISTER
DQ
FF
CK Q
Q2
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
DQ
FF
CK Q
POLARITY
INVERSION
REGISTER
NOTE: At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input. The input voltage may be raised
above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled,
depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance paths that exist between the
pin and either VDD or VSS.
OUTPUT PORT
REGISTER DATA
VDD
ESD PROTECTION DIODE
I/O0 TO I/O7
ESD PROTECTION DIODE
VSS
INPUT PORT
REGISTER DATA
TO INT
POLARITY
REGISTER DATA
SU01784
2004 Sep 30
5
5 Page Philips Semiconductors
8-bit I2C and SMBus low power I/O port with interrupt
Product data sheet
PCA9534
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
P
tHD;STA
S tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Sr
Figure 13. Definition of timing
tSU;STO
P
SU00645
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I2C-bus
MIN MAX
fSCL Operating frequency
0 100
tBUF Bus free time between STOP and START conditions
4.7
—
tHD;STA
Hold time after (repeated) START condition
4.0 —
tSU;STA
Repeated START condition setup time
4.7 —
tSU;STO
Setup time for STOP condition
4.0 —
tHD;DAT
tVD;ACK
tVD;DAT
Data in hold time
Valid time for ACK condition2
Data out valid time3
0—
0.3 3.45
300 —
tSU;DAT
Data setup time
250 —
tLOW
Clock LOW period
4.7 —
tHIGH
Clock HIGH period
4.0 —
tF Clock/Data fall time
— 300
tR Clock/Data rise time
— 1000
tSP Pulse width of spikes that must be suppressed by the —
input filters
50
Port Timing
tPV Output data valid
tPS Input data setup time
tPH Input data hold time
Interrupt Timing
— 200
100 —
1—
tIV Interrupt valid
tIR Interrupt reset
—4
—4
NOTES:
1. Cb = total capacitance of one bus line in pF.
2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
FAST MODE
I2C-bus
MIN MAX
0 400
1.3 —
0.6 —
0.6 —
0.6 —
0—
0.1 0.9
50 —
100 —
1.3 —
0.6 —
20 + 0.1 Cb1
20 + 0.1 Cb1
—
300
300
50
— 200
100 —
1—
—4
—4
UNITS
kHz
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
µs
µs
2004 Sep 30
11
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet PCA9534.PDF ] |
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