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PDF PCA9540D Data sheet ( Hoja de datos )
| Número de pieza | PCA9540D | |
| Descripción | 2-channel I2C multiplexer | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
PCA9540
2-channel I2C multiplexer
Product specification
1999 Dec 15
Philips
Semiconductors
1 page  
Philips Semiconductors
2-channel I2C multiplexer
Product specification
PCA9540
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
S
not acknowledge
acknowledge
12
8
START condition
Figure 4. Acknowledgement on the I2C-bus
9
slave address
1110 0 00
fixed
hardware selectable
Figure 5. Slave address
SW00564
clock pulse for
acknowledgement
SDA
X XX X X X X XX X XX X XXX
SCL
12 34 5 67 89 1234 5 67 89
SLAVE ADDRESS
CONTROL REGISTER
SDA S 1 1 1 0 0 0 0 0 A X X X X X B2 B1 B0 A P
start condition
R/W acknowledge
from slave
acknowledge
from slave
PREVIOUS CHANNEL
Figure 6. WRITE control register
NEW CHANNEL
tpv
SW00498
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA S 1 1 1 0 0 0 0 1 A X X X X X B2 B1 B0 NA P
start condition
R/W acknowledge
from slave
Figure 7. READ control register
no acknowledge
from master
stop condition
SW00499
SW00368
1999 Dec 15
5
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