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PDF BU9252F Data sheet ( Hoja de datos )
| Número de pieza | BU9252F | |
| Descripción | Audio digital delay (KARAOKE echo) | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Multimedia ICs
Audio digital delay (KARAOKE echo)
BU9252S / BU9252F
The BU9252S and BU9252F are digital delays specifically for Karaoke systems. Each has an internal sample hold
circuit, an 8-bit A / D and D / A converter and 2kB SRAM, and allows for the selection of one of eight delay times just
by attaching an inexpensive ceramic resonator.
A digital echo system can be formed by using either of these ICs together with the BA7725S or BA7725FS.
•Applications
Karaoke echo system
Electronic circuits that require signal delays
•Features
1) Internal digital delay circuit.
2) Internal 8-bit A / D converter. Sample rate. (14.22kHz
when fOSC = 455kHz).
3) Internal 2k bytes data SRAM.
4) Internal 8-bit D / A converter.
5) CMOS design for low power consumption.
6) Internal sample hold circuit.
7) Internal feedback resistors and capacitors for oscilla-
tor circuits.
•Block diagram
TEST CIRCUIT
8 × 2k SRAM
ADDRESS COUNTER
AND
MAIN TIMING
1
1 page  
Multimedia ICs
•Circuit operation
(1) External capacitor for signal input pin
Audio signals compressed by the BA7725S or
BA7725FS have their DC component removed by an
AC coupling capacitor and are then input to pin 2 of
BU9252S or BU9252F. At this stage, level deviations
occur because the input signal is capacitor-divided by
this AC coupling capacitor C28 and by sampling hold
capacitor C27 connected to pin 1.
To prevent this, make sure that C27 is much lower
than C28.
(Note: The numbers of external components are the numbers used in the sys-
tem application example.)
C27
1
C28
2 S/H
The sample-held analog signal is converted to digital
by the serial 8-bit A / D converter and then temporarily
stored in the internal SRAM (2k bytes).
(2) Relationship between oscillation frequency (CLK)
and delay time
Sample rate F = fOSC / 32 (fosc: oscillation frequency)
F = 14.22kHz at fosc = 455kHz
Sample period T = 1 / F
Delay time Dtime = T × number of counts
BU9252S / BU9252F
(3) Delay timer settings
The delay time (i.e., the length of time the signal is
stored in the SRAM) can be set to any of eight settings
between the maximum and minimum delay times by
setting pins 6, 7 and 8 to the combination of logic sig-
nal inputs that results in the corresponding number of
counts. The maximum and minimum delay times are
determined by the oscillation frequency of the attached
ceramic resonator.
(dB)
C CC
C : Delay time (ms)
(t)
The delay time can be set to any of the eight settings shown below by setting the logic inputs of terminals DCNT0
through DCNT2.
DCNT1
Logic input
DCNT2
DCNT0
Count
Delay time (ms) (when fOSC = 455kHz)
BU9252S / F
BU9252S / F
000
256
18.00
001
512
36.01
010
768
54.01
011
1024
72.02
100
1280
90.02
101
1536
108.03
110
1792
126.03
111
2048
144.04
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet BU9252F.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
| BU9252F | Audio digital delay (KARAOKE echo) | ROHM Semiconductor |
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