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PDF BU9877FV Data sheet ( Hoja de datos )
| Número de pieza | BU9877FV | |
| Descripción | Serial interface IC for DIMMs supporting plug & play | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Memory ICs
Serial interface IC for DIMMs sup-
porting plug & play
BU9877FV
The BU9877FV is a 2-k bit EEPROM with a write protect function, developed for DIMMs (Dual In-line Memory
Modules) containing a synchronous DRAM. This IC stores IDs in memory in order to enable Plug & Play functions.
•Applications
168-pin and 144-pin DRAM modules containing syn-
chronous DRAM
•Features
1) 2-k bit EEPROM with configuration of 256 words × 8
bits.
2) Compliance with SPD data format.
3) Dual-line serial (I2C bus) interface.
4) Protective functions enabled by a one-time ROM
and write protect pin.
Soft ware protection. as a one-time ROM: 00 to 7Fh.
Hard ware protection (WP pin): 80 to FFh.
5) Compact SSOP-B 8-pin package.
•Absolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Limits
Applied voltage
Power dissipation
VCC – 0.3 ~ + 7.0
Pd 300∗
Storage temperature
Tstg
– 65 ~ + 125
Operating temperature
Topr
– 40 ~ + 85
Input voltage
— – 0.3 ~ VCC + 0.3
∗1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
•Recommended operating conditions (Ta = 25°C)
Parameter
Symbol
Limits
Power supply voltage
VCC
2.7 ~ 5.5
Input voltage
VIN 0 ~ VCC
Unit
V
mW
°C
°C
V
Unit
V
V
1
1 page  
Memory ICs
BU9877FV
•Operation timing characteristics (unless otherwise noted, Ta = – 40 to + 85°C , Vcc = 2.7V to 5.5V)
Parameter
Symbol Min. Typ. Max. Unit
Data clock HIGH time
t HIGH
4.0
—
—
µs
Data clock LOW time
t LOW
4.7
—
—
µs
SDA / SCL rise time
t R — — 1.0 µs
SDA / SCL fall time
Start condition hold time
t F — — 0.3 µs
t HD: STA 4.0 — — µs
Start condition setup time
t SU: STA 4.7 — — µs
Input data hold time
t HD: DAT 0
— — ns
Input data setup time
t SU: DAT 250
—
—
ns
Output data delay time
t PD — — 3.5 µs
Output data hold time
t DH 0.3 — — µs
Stop condition setup time
t SU:STO 4.7 — — µs
Bus release time prior to start of transfer
Internal write cycle time
∗1
∗2
t BUF
4.7
—
—
µs
t WR1
—
—
10 ms
t WR2
—
—
15 ms
Effective noise elimination interval (SCL, SDA pins)
tI
— — 0.1 µs
∗1 VCC = 4.5V to 5.5V
∗2 VCC = 2.7V to 5.5V
(3) Start condition (start bit recognition)
Before executing the various commands, a start condi-
tion (start bit) must be input. This is recognized when
SCL is HIGH and SDA falls from HIGH to LOW.
If a start condition is not input, no commands will be
received.
(4) Stop condition (stop bit recognition)
To terminate the various commands, a stop condition
(stop bit) must be input. This is recognized when SCL
is HIGH and SDA rises from LOW to HIGH.
(5) Precautions concerning the write command
With the write command, internal writing is initiated by
inputting the stop bit after the data has been input.
(6) Device addressing (specifying the slave address)
The master address should be output first, followed by
the start condition, and then the slave address. The
first four bits of the slave address are used to recog-
nize the device type. The device code for this IC is
fixed at "1010". When accessing the write protect regis-
ter, a device code of "0110" is used.
The next three bits of the slave address (A2, A1, A0)
are used to select the device, and the IC begins to
function only if the data input for A2 to A0 matches the
states of input pins A2 to A0. Consequently, up to eight
of these ICs may be connected on the same bus,
depending on the combination of A2 to A0.
The last bit of the slave address (R / W) is used to
specify either writing or reading, and is as shown
below.
R / W set to 0: Writing or Random Read
R / W set to 1: Reading
Device type
1010
0110
Device address
A2 A1 A0
A2 A1 A0
R / W Access to memory
W Access to write protect register
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet BU9877FV.PDF ] | |
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