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Número de pieza | BUJ103AU | |
Descripción | Silicon Diffused Power Transistor | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de BUJ103AU (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! Philips Semiconductors
Silicon Diffused Power Transistor
Product specification
BUJ103AU
GENERAL DESCRIPTION
High-voltage, high-speed planar-passivated npn power switching transistor in the SOT533 envelope intended for
use in high frequency electronic lighting ballast applications, converters, inverters, switching regulators, motor
control systems, etc.
QUICK REFERENCE DATA
SYMBOL
VCESM
VCBO
VCEO
IC
ICM
Ptot
VCEsat
hFEsat
tf
PARAMETER
Collector-emitter voltage peak value
Collector-base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
D.C. current gain
Fall time
CONDITIONS
VBE = 0 V
Tmb ≤ 25 ˚C
IC = 3.0 A;IB = 0.6 A
IC = 3.0 A; VCE = 5 V
IC = 2.5 A; IB1= 0.4 A
TYP.
-
-
-
-
-
-
0.25
12.5
46
MAX.
700
700
400
4
8
50
1.0
-
60
UNIT
V
V
V
A
A
W
V
ns
PINNING - SOT533
PIN DESCRIPTION
1 base
2 collector
3 emitter
tab collector
PIN CONFIGURATION
12
Top view
3
MBK915
SYMBOL
c
b
e
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VCESM
VCEO
VCBO
IC
ICM
IB
IBM
Ptot
Tstg
Tj
Collector to emitter voltage
Collector to emitter voltage (open base)
Collector to base voltage (open emitter)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Total power dissipation
Storage temperature
Junction temperature
VBE = 0 V
Tmb ≤ 25 ˚C
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Junction to mounting base
Junction to ambient
CONDITIONS
in free air
MIN.
-
-
-
-
-
-
-
-
-65
-
MAX.
700
400
700
4
8
2
4
50
150
150
UNIT
V
V
V
A
A
A
A
W
˚C
˚C
TYP.
-
70
MAX.
2.5
-
UNIT
K/W
K/W
October 1999
1
Rev 1.100
1 page Philips Semiconductors
Silicon Diffused Power Transistor
Product specification
BUJ103AU
10 Zth j-mb / (K/W)
D=
1 0.5
0.2
0.1
0.05
0.1
0.02
0
0.01
10us
PD
1ms
t/s
tp
D
=
tp
T
Tt
0.1s 10ms
Fig.13. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
ton/toff (ns)
10,000
5,000
3,000
2,000
toff
100C
1,000
500
ton 25C
300
200 IC/IB = 5
100
123456
IC/A
Fig.14. Resistive Switching.
ton,toff = f(IC).
tfi/tsi (ns)
5,000
2,000
100C
1,000
500
200
100
50
tsi
IC/IB = 5
tfi
25C
20
10
123456
IC/A
Fig.15. Inductive switching.
ton, toff = f(IC)
VCC
IBon
-VBB
LC
LB
VCL(RBSOAR)
PROBE POINT
T.U.T.
Fig.16. Test Circuit for reverse bias safe operating
area.
Vcl ≤ 700V; Vcc = 150V; VBB = -5V; LB = 1µH; Lc =
200µH
IC (A)
9
8
7 VBE=-5V
6
5
4
3
2
1
0
0 100 200 300 400 500 600 700 800 900
VCEclamp (V)
Fig.17. Reverse bias safe operating area Tj ≤ Tjmax
October 1999
5
Rev 1.100
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet BUJ103AU.PDF ] |
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