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PDF BUK104-50S Data sheet ( Hoja de datos )
| Número de pieza | BUK104-50S | |
| Descripción | PowerMOS transistor Logic level TOPFET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK104-50L/S
BUK104-50LP/SP
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 5 pin plastic
envelope, intended as a general
purpose switch for automotive
systems and other applications.
APPLICATIONS
General controller for driving
lamps
motors
solenoids
heaters
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
SYMBOL
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
VIS = 5 V
VIS = 7 V
PARAMETER
VPSN
Protection supply voltage
BUK104-50L
BUK104-50S
MAX.
50
15
40
150
125
100
NOM.
UNIT
V
A
W
˚C
mΩ
mΩ
UNIT
5V
10 V
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Logic and protection supply
from separate pin
Low operating supply current
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by protection supply
Protection circuit condition
indicated by flag pin
5 V logic compatible input level
Separate input pin
for higher frequency drive
ESD protection on input, flag
and protection supply pins
Over voltage clamping for turn
off of inductive loads
Both linear and switching
operation are possible
FUNCTIONAL BLOCK DIAGRAM
PROTECTION SUPPLY
FLAG
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
Fig.1. Elements of the TOPFET.
DRAIN
POWER
MOSFET
SOURCE
PINNING - SOT263
PIN DESCRIPTION
1 input
2 flag
3 drain
4 protection supply
5 source
tab drain
PIN CONFIGURATION
SYMBOL
tab
1 2345
leadform
263-01
Fig. 2. Type numbers ending with
suffix P refer to leadform 263-01.
TOPFET
P
FP
I
D
S
Fig. 3.
January 1993
1
Rev 1.200
1 page  
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK104-50L/S
BUK104-50LP/SP
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
Normal operation
VIS(TO)
Input threshold voltage
IIS
V(CL)IS
RISL
Input current
Input clamp voltage
Overload protection latched
Input resistance1
Application information
External input resistances for
RIS internal overvoltage clamping2
RI internal overload protection3
CONDITIONS
VDS = 5 V; ID = 1 mA
Tmb = 150 ˚C
VIS = 10 V
II = 1 mA
VPS = 5 V
VPS = 10 V
(see figure 29)
RI = ∞ Ω;
RIS = ∞ Ω;
II = 5 mA;
Tmb = 150 ˚C
II = 5 mA;
Tmb = 150 ˚C
VDS > 30 V
VII = 5 V
VII = 10 V
MIN. TYP. MAX. UNIT
1.0 1.5 2.0 V
0.5 - - V
- 10 100 nA
11 13
-
V
- 55 - Ω
- 95 - Ω
- 35 - Ω
- 60 - Ω
100 -
1-
2-
-Ω
- kΩ
- kΩ
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C; RI = 50 Ω; RIS = 50 Ω (see figure 29); resistive load RL = 10 Ω. For waveforms see figure 28.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX.
td on Turn-on delay time
tr Rise time
td off Turn-off delay time
tf Fall time
VDD = 15 V; VIS: 0 V ⇒ 10 V
VDD = 15 V; VIS: 10 V ⇒ 0 V
-8-
- 13 -
- 100 -
- 45 -
UNIT
ns
ns
ns
ns
CAPACITANCES
Tmb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER
Ciss Input capacitance
Coss Output capacitance
Crss Reverse transfer capacitance
Cpso Protection supply pin
capacitance
Cfso Flag pin capacitance
CONDITIONS
VDS = 25 V; VIS = 0 V
VDS = 25 V; VIS = 0 V
VDS = 25 V; VIS = 0 V
VPS = 10 V
VFS = 10 V; VPS = 0 V
MIN.
-
-
-
-
TYP.
415
275
55
30
MAX.
600
400
80
-
UNIT
pF
pF
pF
pF
- 20 - pF
1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.
The external drive circuit should be such that the input voltage does not exceed VIS(TO) minimum when the overload protection has
operated. Refer also to figure for latched input characteristics.
2 Applications using a lower value for RIS would require external overvoltage protection.
3 For applications requiring a lower value for RI, an external overload protection strategy is possible using the flag pin to ‘tell’ the control circuit to
switch off the input.
January 1993
5
Rev 1.200
5 Page 
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
VIS / V & VDS / V
15
VIS
10
BUK104-50L/S
VDS
5
0
0 0.5 1
time / us
Fig.28. Typical resistive load switching waveforms
RI = RIS = 50 Ω; RL = 10 Ω; VDD = 15 V; Tj = 25 ˚C
VII
RI
RIS
D
TOPFET
P
VIS F P
I
S
Fig.29. External input resistances RI and RIS,
generator voltage VII and input voltage VIS.
Capacitance / pF
10000
BUK104-50L/S
1000
100
Ciss
Coss
Crss
10
0
10 20 30 40 50
VDS / V
Fig.30. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VIS = 0 V; f = 1 MHz
Product specification
BUK104-50L/S
BUK104-50LP/SP
Idsr
1 mA
100 uA
10 uA
1 uA
typ.
100 nA
0
20 40 60 80 100 120 140
Tj / C
Fig.31. Typical off-state leakage current.
IDSR = f(Tj); Conditions: VDS = 40 V; RIS = 100 Ω.
Ips normalised to 25 C
1.5
1
0.5
-60 -20 20
60 100 140 180
Tj / C
Fig.32. Normalised protection supply current.
IPS/IPS25 ˚C = f(Tj); VPS = VPSN
January 1993
11
Rev 1.200
11 Page | ||
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| PDF Descargar | [ Datasheet BUK104-50S.PDF ] | |
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