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PDF PCA9550D Data sheet ( Hoja de datos )
| Número de pieza | PCA9550D | |
| Descripción | 2-bit I2C LED driver with programmable blink rates | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
PCA9550
2-bit I2C LED driver with programmable
blink rates
Product data
Supersedes data of 2002 Dec 13
2003 May 02
Philips
Semiconductors
1 page  
Philips Semiconductors
2-bit I2C LED driver with programmable blink rates
Product data
PCA9550
POWER-ON RESET
When power is applied to VDD, an internal Power-On Reset holds
the PCA9550 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9550 registers are
initialized to their default states, all the outputs in the off state.
EXTERNAL RESET
A reset can be accomplished by holding the RESET pin LOW for a
minimum of tW. The PCA9550 registers and I2C state machine will
be held in their default state until the RESET input is once again
HIGH.
This input requires a pull-up resistor to VDD.
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 5).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 5. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 6).
System configuration
A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 7).
SDA
SDA
SCL
S
SCL
P
START condition
STOP condition
Figure 6. Definition of start and stop conditions
SW00365
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
Figure 7. System configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
I2C
MULTIPLEXER
SW00366
2003 May 02
5
5 Page 
Philips Semiconductors
2-bit I2C LED driver with programmable blink rates
Product data
PCA9550
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I2C-BUS
MIN MAX
FAST MODE
I2C-BUS
MIN MAX
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT (L)
tVD;DAT (H)
tSU;DAT
tLOW
tHIGH
tF
tR
tSP
Operating frequency
Bus free time between STOP and START conditions
Hold time after (repeated) START condition
Repeated START condition set-up time
Set-up time for STOP condition
Data in hold time
Valid time for ACK condition2
Data out valid time3
Data out valid time3
Data set-up time
Clock LOW period
Clock HIGH period
Clock/Data fall time
Clock/Data rise time
Pulse width of spikes that must be suppressed by the
input filters
0
4.7
4.0
4.7
4.0
0
—
—
—
250
4.7
4.0
—
—
—
100
—
—
—
—
—
600
600
1500
—
—
—
300
1000
50
0
1.3
0.6
0.6
0.6
0
—
—
—
100
1.3
0.6
20 + 0.1 Cb1
20 + 0.1 Cb1
—
400
—
—
—
—
—
600
600
600
—
—
—
300
300
50
Port Timing
tPV
tPS
tPH
Reset
Output data valid
Input data set-up time
Input data hold time
— 200
100 —
1—
— 200
100 —
1—
tW
tREC
tRESET4,5
Reset pulse width
Reset recovery time
Time to reset
6—
0—
400 —
6—
0—
400 —
NOTES:
1. Cb = total capacitance of one bus line in pF.
2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
4. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
5. Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
UNITS
kHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
2003 May 02
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet PCA9550D.PDF ] | |
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