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PCA9551D 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PCA9551D은 전자 산업 및 응용 분야에서
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부품번호 PCA9551D 기능
기능 8-bit I2C LED driver with programmable blink rates
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PCA9551D 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PCA9551
8-bit I2C LED driver with programmable
blink rates
Product data sheet
Supersedes data of 2003 May 05
2004 Oct 01
Philips
Semiconductors




PCA9551D pdf, 반도체, 판매, 대치품
Philips Semiconductors
8-bit I2C LED driver with programmable blink rates
Product data sheet
PCA9551
BLOCK DIAGRAM
PCA9551
SCL
SDA
INPUT
FILTERS
A2 A1 A0
I2C-BUS
CONTROL
INPUT
REGISTER
LED SELECT (LSx)
REGISTER
VDD
RESET
VSS
POWER-ON
RESET
OSCILLATOR
PRESCALER 0
REGISTER
PRESCALER 1
REGISTER
0
1
PWM0
REGISTER
PWM1
REGISTER
BLINK0
BLINK1
NOTE: ONLY ONE I/O SHOWN FOR CLARITY
Figure 3. Block diagram
LEDx
SW01015
2004 Oct 01
4

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PCA9551D 전자부품, 판매, 대치품
Philips Semiconductors
8-bit I2C LED driver with programmable blink rates
Product data sheet
PCA9551
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
System configuration
A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 8).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL
S
SCL
P
START condition
STOP condition
Figure 7. Definition of start and stop conditions
SW00365
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
Figure 8. System configuration
I2C
MULTIPLEXER
SW00366
2004 Oct 01
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