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S2060B 데이터시트 PDF




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부품번호 S2060B 기능
기능 GIGABIT ETHERNET TRANSCEIVER
제조업체 ETC
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S2060B 데이터시트, 핀배열, 회로
DEVICE
SGPIEGCAIFBICITATEIOTNHERNET TRANSCEIVER
GIGABIT ETHERNET TRANSCEIVER
FEATURES
• Operating rate
• 1250 MHz (Gigabit Ethernet) line rates
• Half and full VCO output rates
• Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
• Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
• Receiver PLL provides clock and data recovery
• 10-bit parallel TTL compatible interface
• Low-jitter serial LVPECL compatible interface
• Local loopback
• Single +3.3 V supply, 620 mW power dissipation
• 64 PQFP or TQFP package
• Continuous downstream clocking from receiver
• Drives 30 m of Twinax cable directly
APPLICATIONS
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
®
S2060
S2060
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
Gigabit
Ethernet
Controller
S2060
Optical
Tx
Optical
Rx
Optical
Rx
Optical
Tx
S2060
Gigabit
Ethernet
Controller
March 7, 2001 / Revision H
1




S2060B pdf, 반도체, 판매, 대치품
S2060
RECEIVER DESCRIPTION
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. The S2060 searches the serial bit stream for
the occurrence of a positive polarity COMMA sync
pattern (0011111xxx positive running disparity) to
perform word synchronization. Once synchronization
on both bit and word boundaries is achieved, the
receiver provides the decoded data on its parallel
outputs.
Clock Recovery Function
Clock recovery is performed on the input data
stream. A simple state machine in the clock recovery
macro decides whether to acquire lock from the se-
rial data input or from the reference clock. The deci-
sion is based upon the frequency and run length of
the input serial data.
The lock to reference frequency criteria ensure that
the S2060 will respond to variations in the serial data
input frequency (as compared to the reference fre-
quency). The new lock state is dependent upon the
current lock state, as shown in Table 3. The run-
length criteria ensure that the S2060 will respond ap-
Table 3. Lock to Reference Frequency Criteria
Current Lock
State
PLL Frequency
(vs. TBC)
New Lock State
< 488 ppm
Locked
Locked
488 to 732 ppm
Undetermined
> 732 ppm
Unlocked
< 244 ppm
Locked
Unlocked
244 to 366 ppm
Undetermined
> 366 ppm
Unlocked
GIGABIT ETHERNET TRANSCEIVER
propriately and quickly to a loss of signal. The run-
length checker flags a condition of consecutive ones
or zeros across 12 parallel words. Thus, 119 or less
consecutive ones or zeros does not cause signal loss,
129 or more causes signal loss, and 120 – 128 may
or may not, depending on how the data aligns across
byte boundaries. If both the off-frequency detect test
and the run-length test is satisfied, the CRU will at-
tempt to lock to the incoming data.
In any transfer of PLL control between the serial
data and the reference clock, the RBC0 and RBC1
remain phase continuous and glitch free, assuring
the integrity of downstream clocking.
Reference Clock Input
The reference clock must be provided from a low
jitter clock source. The frequency of the received
data stream must be within 400 ppm of the reference
clock to ensure reliable locking of the receiver PLL.
A single reference clock is provided to both the
transmit and receive PLL's.
Data Output
The S2060 provides either framed or unframed par-
allel output data, determined by the state of
EN_CDET. With EN_CDET held ACTIVE, the S2060
will detect and align to the 8B/10B COMMA
codeword anywhere in the data stream. When
EN_CDET is INACTIVE, no attempt is made to syn-
chronize on any particular incoming character. The
S2060 will achieve bit synchronization within 250 bit
times and begin to deliver unframed parallel output
data words whenever it has received full transmis-
sion words. Upon change of state of the EN_CDET
input, the COM_DET output response will be de-
layed by a maximum of 3 byte times.
4 March 7, 2001 / Revision H

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S2060B 전자부품, 판매, 대치품
GIGABIT ETHERNET TRANSCEIVER
S2060
Table 5. Pin Description and Assignment (Continued)
Pin Name
Level I/O Pin #
Description
RX[9]
RX[8]
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
LVTTL O
34 Receive Data Outputs. For full rate output, parallel data on this bus
35 is valid on the rising edges of RBC0 and RBC1. RX[0] is the first
36 bit received.
38
39
40
41
43
44
45
RBC1
RBC0
LVTTL O
30 Complementary Receive Byte Clocks. In full rate mode, parallel
31 receive data is valid on the rising edges of RBC0 and RBC1 (see
Figure 8, timing diagram). For half rate, output data is valid on the
rising edge of RBC1. See Table 4.
COM_DET
LVTTL O
47 Comma Detect. Active High. When EN_CDET is active,
COM_DET indicates that the sync character is present on the
parallel bus bits RX[0:9]. Upon detection of the COMMA sync
character (0011111xxx positive polarity) this output data is valid
on the rising edge of RBC1 and remains active for one RBC1 clock
period. When EN_CDET is inactive, COM_DET is held inactive
(logic 0). Upon change of state of the EN_CDET input, the
COM_DET output response will be delayed by a maximum of 3
byte times.
TXP
TXN
Diff. O
LVPECL
62 Transmit Serial Data. These lines are static (TXN HIGH, TXP
61 HIGH) when EWRAP is active. These lines are static (TXN HIGH,
TXP LOW) when TXRST is active. Upon startup, these outputs are
held static (TXN HIGH, TXP LOW) until the TXPLL has locked to
the reference clock. Each output can drive 150 to ground.
S2060A, S2060B, S2060D Specific Pins
DNC
16, 17, Not connected. Note that pin 48 cannot be tied high. It must be
48, 49 open or held low.
S2060C Specific Pins
TC1 16 Transmit Capacitor. External capacitor connections for transmitter
TC0 17 internal PLL filter. The recommended valueof this external
capacitor is 2 nF (a value of 1 nF can also be used). If desired, the
external capacitor may be omitted with no loss in performance.
RC0
RC1
48 Receiver Capacitor. External capacitor connections for receiver
49 internal PLL filter. The recommended value of this external
capacitor is 2 nF (a value of 1 nF can also be used). If desired, the
external capacitor may be omitted with no loss in performance.
Note that pin 48 cannot be tied high. It must be open (as
recommended with external capacitor) or held low.
Note: All TTL inputs have internal 15 Kpull-up networks.
March 7, 2001 / Revision H
7

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