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PCD3312C 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PCD3312C은 전자 산업 및 응용 분야에서
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부품번호 PCD3312C 기능
기능 DTMF/modem/musical-tone generators
제조업체 NXP Semiconductors
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PCD3312C 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCD3311C; PCD3312C
DTMF/modem/musical-tone
generators
Product specification
Supersedes data of May 1990
File under Integrated Circuits, IC03
1996 Nov 21




PCD3312C pdf, 반도체, 판매, 대치품
Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
5 BLOCK DIAGRAM
handbook, full pagewidth
OSCI OSCO
1(3) 2(4)
OSCILLATOR
CLOCK
GENERATOR
3
MODE
4
D5
12
D4
11
D3
INPUT
10 CONTROL
D2 LOGIC
9(8)
D1/SDA
8(7)
D0/SCL
5
STROBE
HIGH
GROUP
DIVIDER
DIVIDER
SELECTION
(ROM)
LOW
GROUP
DIVIDER
SWITCHED
CAPACITOR
BANDGAP
VOLTAGE
REFERENCE
DAC
HIGH
ADDER
DAC
LOW
7(6)
A0
The un-parenthesised numbers are for the PCD3311CP, those in parenthesis for the PCD3312C.
Fig.1 Block diagram.
VDD
VSS
14(2) 13(1)
(5)6
TONE
SWITCHED RESISTOR
CAPACITOR CAPACITOR
PCD3311C
PCD3312C
MGG543
6 PINNING INFORMATION
6.1 Pinning PCD3311CP
handbook, halfpage
OSCI 1
OSCO 2
MODE 3
14 VDD
13 VSS
12 D4
D5 4 PCD3311CP 11 D3
STROBE 5
10 D2
TONE 6
9 D1/SDA
A0 7
8 D0/SCL
MGG508
Fig.2 Pin configuration PCD3311CP.
1996 Nov 21
6.2 Pin description PCD3311CP
SYMBOL PIN TYPE
DESCRIPTION
OSCI
1 I oscillator input
OSCO
2 O oscillator output
MODE 3 I mode select input (selects
I2C or parallel data input)
D5 4 I parallel data input
STROBE
5
I strobe input (for loading
data in parallel mode)
TONE
6 O frequency output (DTMF,
modem, musical tones)
A0
D0/SCL
7
8
I slave address input (to be
connected to VDD or VSS)
I parallel data input or
I2C-bus clock line
D1/SDA
9
I parallel data input or
I2C-bus data line
D2 D4 10 12 I parallel data inputs
VSS 13 P negative supply
VDD 14 P positive supply
4

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PCD3312C 전자부품, 판매, 대치품
Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
handbook, full pagewidth
STROBE
D0
90%
10%
tDS
tSPW
tDH
D1
D2
D3
D4
D5
TONE
MGG511
ttone (ON)
oscillator OFF
oscillator ON
no output tone
oscillator ON
output tones
Fig.5 Timing of STROBE, parallel data inputs and TONE output (770 Hz + 1477 Hz in example) in the parallel
mode (MODE = HIGH).
7.6 I2C-bus clock and data inputs
SCL and SDA are the serial clock and serial data inputs
according to the I2C-bus specification, see Chapter 8.
SCL and SDA must be pulled up externally to VDD.
For the PCD3311C, SCL and SDA are combined with
parallel inputs D0 and D1 respectively - D0/SCL and
D1/SDA operate serially only when MODE is LOW.
7.7 Address input
Address input A0 defines the least significant bit of the
I2C-bus address of the device (see Fig.6). The first 6 bits
of the address are fixed internally. By tying the A0 of each
device to VDD (HIGH) and VSS (LOW) respectively, two
different PCD3311C or PCD3312C devices can be
individually addressed on the bus.
Whether one or two devices are used, A0 must be
connected to VDD or VSS.
7.8 I2C-bus data configuration (see Fig.6)
The PCD3311C and PCD3312C are always slave
receivers in the I2C-bus configuration. The R/W bit in is
thus always LOW, indicating that the master
(microcontroller) is writing.
The slave address in the serial mode consists of 7 bits: 6
bits internally fixed, 1 externally set via A0. in the serial
mode, the same input data codes are used as in the
parallel mode. See Tables 2, 3, 4 and 5.
7.9 Tone output
The single and dual tones provided at the TONE output are
first filtered by an on-chip switched-capacitor filter,
followed by an active RC low-pass filter. The filtered tones
fulfil the CEPT recommendations for total harmonic
distortion of DTMF tones. An on-chip reference voltage
provides output tone levels independent of the supply
voltage. Tables 3, 4 and 5 give the frequency deviation of
the output tones with respect to the standard DTMF,
modem and music frequencies.
1996 Nov 21
7

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