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PCD3332-2T 데이터시트 PDF




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부품번호 PCD3332-2T 기능
기능 Multistandard pulse/tone repertory diallers/ringers
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PCD3332-2T 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCD3332-2; PCD3332-3;
PCD3332-S
Multistandard pulse/tone repertory
diallers/ringers
Product specification
File under Integrated Circuits, IC03
1997 Jan 13




PCD3332-2T pdf, 반도체, 판매, 대치품
Philips Semiconductors
Multistandard pulse/tone repertory
diallers/ringers
Product specification
PCD3332-2; PCD3332-3;
PCD3332-S
4 PINNING
4.1 PCD3332-2
SYMBOL
ROW2
ROW3
ROW4
ROW5
DIODE
MUTE
EARTH
CSI
XTAL1
XTAL2
RESET
CE/FDI
COL6
COL5
COL4
COL3
COL2
COL1
DP/FL
not used
VOL2
VSS
TONE
VDD
VOL1
DMO/KTE
RTE
ROW1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TYPE
I/O(1)
I/O(1)
I/O(1)
O(2)
I/O(1)
O(4)
O(4)
I
I
O
I
I
I/O(1)
I/O(1)
I/O(1)
I/O(1)
I/O(1)
I/O(1)
O(2)
O(4)
O(3)
P
O
P
O(3)
O(4)
O(4)
I/O(1)
DESCRIPTION
row 2 keyboard output
row 3 keyboard output
row 4 keyboard output
row 5 keyboard output
diode option
mute output
earth recall
cradle switch input
oscillator input
oscillator output
reset input
chip enable/frequency discriminator
column 6 input
column 5 input
column 4 input
column 3 input
column 2 input
column 1 input
dial pulse/flash output
not used, leave pin unconnected
volume 2 output
ground
tone generator output
positive supply voltage
volume 1 output
dial mode output
key/ringer tone enable
row 1 keyboard output
Notes on types and initial states of inputs and outputs
1. Standard input or output, set to HIGH state.
2. Open-drain output, set to HIGH state.
3. Open-drain output, reset to LOW state.
4. Push-pull output, reset to LOW state.
age
ROW2 1
28 ROW1
ROW3 2
27 RTE
ROW4 3
26 DMO/KTE
ROW5 4
25 VOL1
DIODE 5
MUTE 6
24 VDD
23 TONE
EARTH 7
22 VSS
PCD3332-2
CSI 8
21 VOL2
XTAL1 9
20 not used
XTAL2 10
19 DP/FL
RESET 11
18 COL1
CE/FDI 12
17 COL2
COL6 13
16 COL3
COL5 14
15 COL4
MBE757
Fig.1 Pin configuration.
1997 Jan 13
4

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PCD3332-2T 전자부품, 판매, 대치품
Philips Semiconductors
Multistandard pulse/tone repertory
diallers/ringers
Product specification
PCD3332-2; PCD3332-3;
PCD3332-S
5 FUNCTIONAL DESCRIPTION
References to the ‘PCD3332’ or the ‘device’ apply to the
PCD3332-2, the PCD3332-3 and the PCD3332-S.
5.1 Pin description
5.1.1 SUPPLY TERMINALS (VDD AND VSS)
To retain data in the RAM, the standby supply voltage of
1 V, must be maintained. To ensure that the contents of
the RAM are secure in the event of a power failure, a
capacitor may be connected across the supply terminals.
The capacitor must have a suitable value to maintain the
standby voltage for a certain period of time. The minimum
operating voltage of these devices is 2.5 V. The internal
power-on reset is enabled for a voltage below this
minimum operating voltage.
5.1.2 OSCILLATOR INPUT/OUTPUT (XTAL1 AND XTAL2)
The time base for the PCD3332 is a crystal-controlled
on-chip oscillator, which incorporates a 3.58 MHz crystal
or ceramic resonator connected between XTAL1 and
XTAL2. It should be noted that when using a ceramic
resonator, the minimum supply voltage increases.
The oscillator starts when VDD reaches its operating
voltage level and CE = HIGH (min. 2.5 V).
5.1.3
CHIP ENABLE AND FREQUENCY DISCRIMINATOR
INPUT (CE/FDI)
For DC inputs this pin acts as the chip enable (CE) input,
and is active HIGH. CE in combination with the Cradle
Switch Input (CSI) determines the mode of the device.
See Table 1.
For AC inputs the pin acts as the (ringer) Frequency
Discriminator Input (FDI).
To generate a correct ringer output tone, the input
frequency must be between 19.5 Hz and 57 Hz;
frequencies below 18 Hz and higher than 64 Hz are
omitted.
The PCD3332-3 has a second (diode selectable) range of
valid input frequencies of 14.5 Hz to 68 Hz; frequencies
below 14 Hz and higher than 76 Hz are omitted.
Ringer response timing and detection is illustrated in
Fig.15.
5.1.4 CRADLE SWITCH INPUT (CSI)
CSI is normally generated from the physical ‘off-hooking’
of the phone. CSI in combination with CE/FDI determines
the operating mode of the PCD3332, as shown in Table 1.
Table 1 Different modes of the PCD3332
INPUT CSI
LOW
HIGH
LOW
HIGH
INPUT CE/FDI
LOW
LOW
HIGH
HIGH
PCD3332 STATUS
stop or power-down
mode
idle mode
ringer mode
conversation or
off-hook mode
5.1.5 RESET INPUT (RESET)
RESET activates the on-chip reset circuit and is active
HIGH. The reset circuit initializes all inputs and outputs.
Two other events will cause the chip to initialize:
CE going HIGH
VDD falling below 2.5 V, then being restored (power-on
reset).
For this reason, RESET may not be required, and can be
connected to VSS. This should preferably be via a 100 k
resistor, to save leakage current.
Note that a suitable capacitor connected between VDD and
VSS will inhibit the decrease of voltage at VDD after a power
failure, and thus extend the time until the power-on reset is
initiated.
5.1.6 PULSE DIAL AND FLASH OUTPUT (DP/FL)
This pin is the output for:
The dial pulse sequence (DP)
The calibrated LOW pulse (FL) after the FLASH key is
pressed.
The dialling sequence for pulse dialling is shown in Figs 11
and 12. DP/FL starts HIGH, pulses are LOW, and the
inter-digit pauses are HIGH. Thus, DP/FL is HIGH during
a line-make and LOW during a line-break.
If the Flash/Earth diode option is set to FLASH, then when
FLASH is pressed a LOW pulse is output, with a calibrated
duration also determined by diode option.
1997 Jan 13
7

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