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PCD5002 데이터시트 PDF




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부품번호 PCD5002 기능
기능 Advanced POCSAG and APOC-1 Paging Decoder
제조업체 NXP Semiconductors
로고 NXP Semiconductors 로고


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PCD5002 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCD5002
Advanced POCSAG and APOC-1
Paging Decoder
Product specification
Supersedes data of 1997 Mar 04
File under Integrated Circuits, IC17
1997 Jun 24




PCD5002 pdf, 반도체, 판매, 대치품
Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
6 BLOCK DIAGRAM
Product specification
PCD5002
handbook, full pagewidth
ZSD
ZSC
ZLE
RXE
ROE
26
27 SYNTHESIZER
28 CONTROL
24
RECEIVER
25 CONTROL
DATA FILTER
23
RDI
AND
CLOCK
RECOVERY
DON
3
CLOCK
CONTROL
16
TS1 TEST
TS2 20 CONTROL
XTAL1
18
XTAL2
17
EEPROM
RESET
SET-UP
7
EEPROM CONTROL
DECODING
DATA
CONTROL
POCSAG
SYNCHRONIZATION
MAIN DECODER
MASTER
DIVIDER
TIMER
REFERENCE
OSCILLATOR
PCD5002
RAM
CONTROL
I2C-BUS
CONTROL
9
10
REGISTERS
AND
INTERRUPT
CONTROL
5
21
RAM
ALERT
GENERATION
AND
CONTROL
30
31
1
32
2
4
VOLTAGE
DOUBLER
AND LEVEL
SHIFTER
15
14
13
8
11 12, 29
VDD VSS
MGD081
RST
SDA
SCL
INT
BAT
VIB
LED
ATL
ATH
ALC
REF
CCN
CCP
VPO
VPR
1997 Jun 24
Fig.1 Block diagram.
4

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PCD5002 전자부품, 판매, 대치품
Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
Address codewords are identified by an MSB at logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address codeword (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
Four different call types (‘numeric’, ‘alphanumeric’ and two
‘alert only’ types) can be distinguished. The call type is
determined by two function bits in the address codeword
(bits 20 and 21), as shown in Table 1.
Alert-only calls consist only of a single address codeword.
Numeric and alphanumeric calls have message
codewords following the address. A message causes the
frame structure to be temporarily suspended. Message
codewords are sent until the message is completed, with
only the sync words being transmitted in their expected
positions.
Message codewords are identified by an MSB at logic 1
and are coded as shown in Fig.3. The message
information is stored in a 20-bit field (bits 2 to 21).
The standard data format is determined by the call type: 4
bits per digit for numeric messages and 7 bits per (ASCII)
character for alphanumeric messages.
Each codeword is protected against transmission errors by
10 CRC check bits (bits 22 to 31) and an even-parity bit
(bit 32). This permits correction of a maximum of 2 random
errors or up to 3 errors in a burst of 4 bits (a 4-bit burst
error) per codeword.
8.3 The APOC-1 paging code
The APOC-1 paging code is fully POCSAG compatible
and involves the introduction of batch grouping and a
Batch Zero Identifier. This reserved address codeword
indicates the start of a ‘cycle’ of 5 or 15 batches long and
is transmitted immediately after a sync word.
Cycle transmission must be coherent i.e. a transmission
starting an integer number of cycle periods after the start
of the previous one.
Broadcast message data may be included in a
transmission. This information may occupy any number of
message codewords and immediately follows the batch
zero identifier of the first cycle after preamble.
The presence of data is indicated by the function bits in the
batch zero identifier: 1,1 indicates ‘no broadcast data’.
Any other combination indicates a broadcast message.
The PCD5002 can be configured for POCSAG or APOC-1
operation via SPF programming. The batch zero identifier
is programmable and can be stored in any identifier
location in EEPROM.
handbook, full pagewidth
PREAMBLE BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0 FRAME 1
FRAME 7
Address code-word 0 18-bit address 2 function bits 10 CRC bits P
Message code-word 1 20-bit message
10 CRC bits P
MCD456
1997 Jun 24
Fig.3 POCSAG code structure.
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