Datasheet.kr   

ULTRA37000 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 ULTRA37000은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ULTRA37000 자료 제공

부품번호 ULTRA37000 기능
기능 5V/ 3.3V/ ISR High-Performance CPLDs
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


ULTRA37000 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

ULTRA37000 데이터시트, 핀배열, 회로
Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
General Description
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
• High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI-compatible[1]
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and In-
System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-
compliant serial interface. Data is shifted in and out through
the TDI and TDO pins, respectively. Because of the superior
routability and simple timing model of the Ultra37000 devices,
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
— Product term sharing among local macrocells
• Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
• Consistent package/pinout offering across all densities
— Simplifies design migration
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. VCCO connections provide the
capability of interfacing to either a 5V or 3.3V bus. By
connecting the VCCO pins to 5V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3V the output levels
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
— Same pinout for 3.3V and 5.0V devices
Ultra37000V 3.3V Devices
• Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
Devices operating with a 3.3V supply require 3.3V on all VCCO
pins, reducing the device’s power consumption. These
BGA, and Fine-Pitch BGA packages
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03007 Rev. *B
Revised May 7, 2003




ULTRA37000 pdf, 반도체, 판매, 대치품
Ultra37000 CPLD Family
FROM
PIM
36
7
72 x 87
PRODUCT TERM
ARRAY
80
016
PRODUCT
TERMS
3
MACRO-
CELL
0
016
PRODUCT
TERMS
MACRO-
CELL
1
PRODUCT
TERM
ALLOCATOR
2
I/O
CELL
0
2
to cells
2, 4, 6 8, 10, 12
016
PRODUCT
TERMS
MACRO-
CELL
14
I/O
CELL
14
016
MACRO-
CELL
TO
PRODUCT
15
PIM
TERMS
16
8
Figure 1. Logic Block with 50% Buried Macrocells
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conser-
vation. The logic block mode is set by the user on a logic block
by logic block basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator
provides two important capabilities without affecting perfor-
mance: product term steering and product term sharing.
variable fashion. The software automatically takes advantage
of this capability—the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All worst-
case steering and sharing configurations have been incorpo-
rated in the timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Ultra37000 devices,
product terms are steered on an individual basis. Any number
between 0 and 16 product terms can be steered to any
macrocell. Note that 0 product terms is useful in cases where
a particular macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator
allows sharing across groups of four output macrocells in a
Buried Macrocell
Figure 2 displays the architecture of buried macrocells. The
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or asynchronously
reset at the logic block level with the separate set and reset
product terms. Each of these product terms features program-
mable polarity. This allows the registers to be set or reset
based on an AND expression or an OR expression.
Clocking of the register is very flexible. Four global
synchronous clocks and a product term clock are available to
clock the register. Furthermore, each clock features program-
mable polarity so that registers can be triggered on falling as
well as rising edges (see the Clocking section). Clock polarity
is chosen at the logic block level.
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
Document #: 38-03007 Rev. *B
Page 4 of 63

4페이지










ULTRA37000 전자부품, 판매, 대치품
Ultra37000 CPLD Family
INPUT/CLOCK PIN
FROM CLOCK
POLARITY INPUT
CLOCK PINS
0
1
2
O
3
C8 C9
D
Q
DQ
LE
D
Q
0
O
1
TO CLOCK MUX ON
ALL INPUT MACROCELLS
C12
0
1
2
O TO PIM
3
C10C11
0
O
1
C13, C14, C15 OR C16
TO CLOCK MUX
IN EACH
LOGIC BLOCK
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
Figure 4. Input/Clock Macrocell
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used. Figure
5 illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input set-
up time to the output macrocells for any input is 3.5 ns and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
The Ultra37000 features:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
INPUT
COMBINATORIAL SIGNAL
tPD = 6.5 ns
OUTPUT
INPUT
REGISTERED SIGNAL
tS = 3.5 ns
D,T,L O
tCO = 4.5 ns
OUTPUT
CLOCK
Figure 5. Timing Model for CY37128
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable
timing model ensures compliance with the PCI AC specifica-
tions independent of the design.
Document #: 38-03007 Rev. *B
Page 7 of 63

7페이지


구       성 총 30 페이지수
다운로드[ ULTRA37000.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ULTRA37000

5V/ 3.3V/ ISR High-Performance CPLDs

Cypress Semiconductor
Cypress Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵