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부품번호 | PCE84C886 기능 |
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기능 | Microcontroller for monitor OSD and auto-sync applications | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 30 페이지수
INTEGRATED CIRCUITS
DATA SHEET
PCE84C886
Microcontroller for monitor OSD
and auto-sync applications
Preliminary specification
File under Integrated Circuits, IC14
1996 Jan 08
Philips Semiconductors
Microcontroller for monitor OSD
and auto-sync applications
4 BLOCK DIAGRAM
Preliminary specification
PCE84C886
handbook, full pagewidth
T1
INTN / T0
VDD
XTAL1 (IN)
XTAL2 (OUT)
8-BIT
TIMER /
EVENT
COUNTER
CPU
VOW0 VOW2 VSYNCN
T3
FB VOW1
C HSYNCN
(3) (3)
8-BIT
COUNTER
ROM
8 kbytes
RAM
192 bytes
ON SCREEN DISPLAY
8-bit internal bus
RESET
TEST / EMU
VSS
PARALLEL
I/O
PORTS
PCF84CXX
core
excluding
ROM / RAM
8-BIT
I/O
PORTS
4 x 6-BIT PWM
4 x 7-BIT PWM
14-BIT
PWM
84
P0 P1
844
DP0 DP1 DP2
(1)
PWM0
to
PWM7
(2)
PWM8
3 x 4-BIT
ADC
I2C-BUS
INTERFACE
(2)
ADC0
to
ADC2
MLC067
(3) (3)
SDA SCL
(1) Alternative function of DP0.
(2) Alternative function of DP1.
(3) Alternative function of DP2.
Fig.1 Block diagram.
1996 Jan 08
4
4페이지 Philips Semiconductors
Microcontroller for monitor OSD
and auto-sync applications
Preliminary specification
PCE84C886
6 RESET
The RESET pin may be used as an active LOW input to
initialize the microcontroller to a defined state.
An active reset can be generated by driving the RESET pin
from an external logic device. Such an active reset pulse
should not fall off before VDD has reached its
fxtal-dependent minimum operating voltage.
A Power-on-reset can be generated using an external RC
circuit. To avoid overload of the internal diode, an external
diode should be added in parallel if CRESET ≥ 2.2 µF. The
RC circuit is shown in Fig.3.
6.1 Reset trip level
The RESET trip voltage level is masked to 1.3 V in the
PCE84C886.
If any input (for example Hsync) goes HIGH before VDD is
applied, latch-up may occur and in this situation the
PCE84C886 cannot be reset. The cause and effect of
latch-up is shown in Fig.4.
6.2 Reset status
• Derivative Registers reset status; see Table 38 for
details
• Program Counter 00H
• Memory Bank 0
• Register Bank 0
• Stack Pointer 00H
• All interrupts disabled
• Timer/event counter 1 stopped and cleared
• Timer pre-scaler modulo-32 (PS = 0)
• Timer flag cleared
• Serial I/O interface disabled (ESO = 0) and in slave
receiver mode
• Idle and Stop mode cleared.
handbook, halfpage
V DD
R RESET
( 100 kΩ)
RESET
C RESET
V SS
internal reset
PCA84C8XX
MLC259
Fig.3 External components for RESET pin.
handbook, halfpage
V DD
V DD
Hsync
R RESET
C RESET
V SS
HSYNCN
V SS
RESET
internal V DD
PCE84C886
internal reset
MLC260
Fig.4 The influence of an active HIGH signal being
applied before Power-on-reset.
1996 Jan 08
7
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
PCE84C882 | Microcontroller For Monitor Osd And Auto-sync Applications | NXP Semiconductors |
PCE84C886 | Microcontroller for monitor OSD and auto-sync applications | NXP Semiconductors |
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