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PCF2113AU PDF 데이터시트 ( Data , Function )

부품번호 PCF2113AU 기능
기능 LCD controller/driver
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PCF2113AU 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
PCF2113x
LCD controller/driver
Product specification
Supersedes data of 1996 Oct 21
File under Integrated Circuits, IC12
1997 Apr 04




PCF2113AU pdf, 반도체, 판매, 대치품
Philips Semiconductors
LCD controller/driver
5 BLOCK DIAGRAM
Product specification
PCF2113x
handbook, full pagewidth
8 BIAS
VLCD1
VOLTAGE
GENERATOR
VLCD2
7
VLCD
GENERATOR
C1 to C60
18 to 77
60
COLUMN DRIVERS
60
DATA LATCHES
60
SHIFT REGISTER 5 × 12 BIT
5
CURSOR AND DATA CONTROL
5
R1 to R18
9 to 17
78 to 86 18
ROW DRIVERS
18
SHIFT REGISTER 18-BIT
OSCILLATOR
2 OSC
1, 100
VDD1, 2
VSS1, 2
5, 6
CHARACTER
GENERATOR
RAM (128 × 5)
(CGRAM)
16 CHARACTERS
8
CHARACTER
GENERATOR
ROM
(CGROM)
240 CHARACTERS
TIMING
GENERATOR
T1 4
7 DISPLAY DATA RAM
(DDRAM)
80 CHARACTERS/BYTES
7
ADDRESS COUNTER
(AC)
77
INSTRUCTION
DECODER
DATA
REGISTER
(DR)
BUSY
FLAG
8
INSTRUCTION
REGISTER
88
I/O BUFFER
96 to 99 92 to 95 89
91 90 87 88
DB0 to DB3/SA0 DB4 to DB7 E R/W RS SCL SDA
7
DISPLAY
ADDRESS
COUNTER
PCF2113x
3
PD
POWER-ON
RESET
MGE990
Fig.1 Block diagram.
1997 Apr 04
4

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PCF2113AU 전자부품, 판매, 대치품
Philips Semiconductors
LCD controller/driver
Product specification
PCF2113x
7 PIN FUNCTIONS
NAME
FUNCTION
DESCRIPTION
RS register select RS selects the register to be accessed for read and write when the device is
controlled by the parallel interface. There is an internal pull-up on this pin.
RS = logic 0 selects the instruction register for write and the Busy Flag and Address
Counter for read.
RS = logic 1 selects the data register for both read and write.
R/W
read/write
R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when
the device is controlled by the parallel interface. There is an internal pull-up on this
pin.
E data bus clock The E pin is set HIGH to signal the start of a read or write operation when the device
is controlled by the parallel interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied to logic 0 (VSS) when
I2C-bus control is used.
DB7 to DB0 data bus
The parallel interface of the device. This bi-directional, 3-state data bus transfers
data between the system controller and the PCF2113x. There is an internal pull-up
on each of the data lines.
DB7 to DB0 must be connected to VDD or left open circuit when I2C-bus control is
used. Note that DB3 shares the same pin as SA0.
In 4-bit operations only DB7 to DB4 are used, and DB3 to DB0 must be left open
circuit. See note 1.
DB7 may be used as the Busy Flag, signalling that internal operations are not yet
completed.
C1 to C60 column driver
outputs
These pins output the data for columns.
R1 to R18 row driver
outputs
These pins output the row select waveforms to the display.
R17 and R18 drive the icons.
VLCD
LCD power
supply
Positive power supply for the liquid crystal display. This may be generated on-chip or
supplied externally.
OSC
SCL
oscillator
serial clock line
When the on-chip oscillator is used this pin must be connected to VDD.
An external clock signal, if used, is input at this pin.
Input for the I2C-bus clock signal.
SDA
serial data line
SCL must be connected to VSS or VDD when the parallel interface is used.
I/O for the I2C-bus data line.
SDA must be connected to VSS or VDD when the parallel interface is used.
SA0
address pin
The hardware sub-address line is used to program the device sub-address for two
different PCF2113xs on the same I2C bus. Note that SA0 shares the same pin as
DB3.
T1
test pad
T1 must be connected to VSS and is not user accessible.
PD power-down pad PD selects chip power-down mode. For normal operation PD = logic 0.
Note
1. If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.
1997 Apr 04
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