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PDF PCF50732H Data sheet ( Hoja de datos )
| Número de pieza | PCF50732H | |
| Descripción | Baseband and audio interface for GSM | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF50732
Baseband and audio interface for
GSM
Objective specification
File under Integrated Circuits, IC17
1999 May 03
1 page  
Philips Semiconductors
Baseband and audio interface for GSM
6 BLOCK DIAGRAM
Objective specification
PCF50732
handbook, full pagewidth
VDDD VDDA(bb) VDDA(vb) VDDA(vbo) VDDA(ref)
7 25 37 47 34
PCF50732
REFERENCE
VOLTAGES AND
CURRENTS
36
Vref
TXON
BIEN
BIOCLK
BDIO
RXON
BOEN
19
16
15
17
20
18
BSI
AUXST
CCLK
CEN
CDI
CDO
AMPCTRL
13
9
10
11
12
14
CSI
ACLK
AFS
ADI
ADO
4
3
2
1
ASI
10
GMSK
MODULATOR
10
10-BIT
DAC
10-BIT
DAC
DIGITAL
FILTER
ADC
ADC
LP
LP
2
M
U
X
23
24
21
22
27
28
29
30
DAC3
CTL
64 × 10-BIT
SRAM
10
12
8
VOICE BAND
SIGNAL
PROCESSOR
DECIMATION
FILTER
IRAM
NOISE
SHAPER
AUXDAC3
10-BIT
AUXDAC2
12-BIT
AUXDAC1
8-BIT
MICADC
2
EARDAC
1 MHz
33
32
31
40
M 41
U 38
X 39
46
OUTPUT
AMPLIFIER 45
QP
QN
IP
IN
AUXADC1
AUXADC2
AUXADC3
AUXADC4
AUXDAC3
AUXDAC2
AUXDAC1
MICP
MICN
AUXMICP
AUXMICN
EARP
EARN
MCLK
RESET
6
5
CLOCK
GENERATOR
8 26 42 48 35
VSSD VSSA(bb) VSSA(vb) VSSA(vbo) VSSA(ref)
OUTPUT 44
AMPLIFIER
OUTPUT 43
AMPLIFIER
AUXSP
BUZ
MGR988
1999 May 03
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
Baseband and audio interface for GSM
Objective specification
PCF50732
20
handbook, full pagewidth
gain
(dB)
0
MBL025
−20
ZIF
−40
NZIF
−60
−80
−100
0
100 200 300 400 500 600
f (kHz)
3
Fig.3 Transfer functions for the baseband receive filter.
9.3 Baseband Serial Interface (BSI)
9.3.1 OVERVIEW
The digital part of the baseband consists of a receive
section and a transmit section. The receive section is a
FIR filter that reduces the 6.5 MHz (13 MHz for
NZIF mode) bitstream from the sigma-delta converters
into 2 × 12-bit values at 270.833 kHz (541.667 kHz for
NZIF mode).
The transmit section converts the 270.833 kHz data
stream from the DSP into a GMSK signal sampled at
4.333 MHz. The 10-bit I and Q signals are then fed into
two 10-bit DACs. The power ramping signal is also
generated by the transmit section with the 10-bit
AUXDAC3 block.
9.3.2 TRANSMIT PATH BLOCK DESCRIPTION
9.3.2.1 Transmit serial interface
The power-up of the BSI transmit path is controlled via the
TXON pin. When TXON is pulled HIGH, the transmit path
recovers from power-down. The MCLK/48 = 270.833 kHz
output signal BIOCLK is activated. When the BIEN0 period
has elapsed the output signal BIEN goes LOW and the bits
to be transmitted are clocked out of the DSP.
BIEN0 must be at least 10 quarterbits long to allow settling
of the analog filters. Bits are clocked out of the DSP by the
falling edge and clocked into the PCF50732 by the rising
edge of BIOCLK. After the BIEN1 period has elapsed,
BIEN is set HIGH again and transmission from the DSP
ends. Logic 1s are modulated whenever BIEN is HIGH
and the baseband transmit (BBTX) block is active. Values
for BIEN0 and BIEN1 can be set in the Burst control
register.
Figure 5 shows the timing for the BSI data transmission.
In power-down the de-asserted value of BIOCLK is high-Z
and BIEN is HIGH. Typical connection to the system DSP
is defined in Table 1.
Table 1 Connection of BSI transmit signals to
PCF5087X
PCF50732
PCF5087X
PIN
TXON
BDIO
BIEN
BIOCLK
I/O PIN I/O
I
RFSIG[y]
O
I/O SIOXD I/O
O SOXEN_N
I
O SIOXCLK
I
1999 May 03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCF50732H.PDF ] | |
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