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UPD16772AN 데이터시트 PDF




NEC에서 제조한 전자 부품 UPD16772AN은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 UPD16772AN 기능
기능 480-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64-GRAY SCALES
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UPD16772AN 데이터시트, 핀배열, 회로
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16772A
480-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD16772A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to UXGA-standard TFT-LCD panels.
FEATURES
CMOS level input (2.3 to 3.6 V)
480 outputs
Input of 6 bits (gradation data) by 6 dots
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-
DAC)
Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V
High-speed data transfer : fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V)
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Display data inversion function (POL21/22)
Current consumption reduction function (LPC, Bcont)
Logic power supply voltage (VDD1) : 2.3 to 3.6 V
Driver power supply voltage (VDD2) : 8.5 V ± 0.5 V
ORDERING INFORMATION
Part Number
µ PD16772AN-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14725EJ1V0DS00 (1st edition)
Date Published August 2000 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
2000




UPD16772AN pdf, 반도체, 판매, 대치품
µPD16772A
4. PIN FUNCTIONS
Pin Symbol
S1 to S480
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
STHR
STHL
CLK
STB
POL
POL21,
POL22
LPC
Bcont
V0 to V9
VDD1
VDD2
VSS1
VSS2
Pin Name
Driver output
Display data input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2
pixels).
DX0: LSB, DX5: MSB
Shift direction control These refer to the start pulse I/O pins when driver ICs are connected in cascade. The shift
input
directions of the shift registers are as follows.
R,/L = H: STHR input, S1 S480, STHL output
R,/L = L: STHL input, S480 S1, STHR output
Right shift start pulse These refer to the start pulse I/O pins when driver ICs are connected in cascade.
input/output
Fetching of display data starts when H is read at the rising edge of CLK.
Left shift start pulse R,/L = H (right shift): STHR input, STHL output
input/output
R,/L = L (left shift): STHL input, STHR output
The start pulse width (H level) for next-level drivers is 1CLK.
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge. At the rising edge of the 80th clock after the start pulse input, the
start pulse output reaches the high level, thus becoming the start pulse of the next-level
driver. If 82 clock pulses are input after input of the start pulse, input of display data is halted
automatically. The contents of the shift register are cleared at the STB’s rising edge.
Latch input
The contents of the data register are transferred to the latch circuit at the rising edge. And,
at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure
input of one pulse per horizontal period.
Polarity input
POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to
V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to
V4 as the reference supply.
S2n–1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is
allowed the setup time(tPOL-STB) with respect to STB’s rising edge.
Data inversion input Data inversion can invert when display data is loaded.
POL21/22 = H : Data inversion loads display data after inverting it.
POL21/22 = L : Data inversion does not invert input data.
POL21: D00 to D05, D10 to D15, D20 to D25
POL22: D30 to D35, D40 to D45, D50 to D55
Low power control
input
The current consumption of VDD2 is lowered by controlling the constant current source of the
output amplifier. This pin is pulled up to the VDD1 power supply inside the IC. For details,
see 9. CURRENT CONSUMPTION REDUCTION FUNCTION.
Bias control
This pin can be used to finely control the bias current inside the output amplifier.
When this fine-control function is not required, leave this pin open. For details, see
9. CURRENT CONSUMPTION REDUCTION FUNCTION.
γ -corrected power
supplies
Input the γ -corrected power supplies from outside by using operational amplifier. Make sure
to maintain the following relationships. During the gray scale voltage output, be sure to keep
the gray scale level power supply at a constant level.
VDD2 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
Logic power supply 2.3 to 3.6 V
Driver power supply 8.5 V ± 0.5 V
Logic ground
Grounding
Driver ground
Grounding
4 Data Sheet S14725EJ1V0DS00

4페이지










UPD16772AN 전자부품, 판매, 대치품
V0
r0
r1
r2
r3
r14
r15
V1
r16
r17
r46
r47
V3
r48
r49
r60
r61
r62
V4
µPD16772A
Figure 5–2. Relationship between Input Data and Output Voltage
VDD2 – 0.2 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2, POL21/22 = L
Data DX5 DX4 DX3 DX2 DX1 DX0
Output votage
V0' 00H 0
0
0
0
0
0 V0'
V0
01H 0
0
0
0
0
1 V1'
V1+(V0-V1)× 6500 /
V1' 02H 0
0
0
0
1
0 V2'
V1+(V0-V1)× 5800 /
03H 0
0
0
0
1
1 V3'
V1+(V0-V1)× 5100 /
V2' 04H 0
0
0
1
0
0 V4'
V1+(V0-V1)× 4400 /
05H 0
0
0
1
0
1 V5'
V1+(V0-V1)× 3700 /
V3' 06H 0
0
0
1
1
0 V6'
V1+(V0-V1)× 3350 /
07H 0
0
0
1
1
1 V7'
V1+(V0-V1)× 3000 /
08H 0
0
1
0
0
0 V8'
V1+(V0-V1)× 2650 /
09H 0
0
1
0
0
1 V9'
V1+(V0-V1)× 2300 /
0AH
0
0
1
0
1
0 V10' V1+(V0-V1)× 1950 /
0BH
0
0
1
0
1
1 V11' V1+(V0-V1)× 1600 /
0CH
0
0
1
1
0
0 V12' V1+(V0-V1)× 1250 /
0DH
0
0
1
1
0
1 V13' V1+(V0-V1)× 900 /
0EH
0
0
1
1
1
0 V14' V1+(V0-V1)× 600 /
V15' 0FH 0 0 1 1 1 1 V15' V1+(V0-V1)× 300 /
10H 0 1 0 0 0 0 V16' V1
V16' 11H 0 1 0 0 0 1 V17 V2+(V1-V2)× 2100 /
12H 0 1 0 0 1 0 V18' V2+(V1-V2)× 1900 /
V17' 13H 0 1 0 0 1 1 V19' V2+(V1-V2)× 1700 /
14H 0 1 0 1 0 0 V20' V2+(V1-V2)× 1500 /
15H 0 1 0 1 0 1 V21' V2+(V1-V2)× 1300 /
16H 0 1 0 1 1 0 V22' V2+(V1-V2)× 1150 /
17H 0 1 0 1 1 1 V23' V2+(V1-V2)× 1000 /
18H 0 1 1 0 0 0 V24' V2+(V1-V2)× 850 /
19H 0 1 1 0 0 1 V25' V2+(V1-V2)× 700 /
1AH
0
1
1
0
1
0 V26' V2+(V1-V2)× 600 /
1BH
0
1
1
0
1
1 V27' V2+(V1-V2)× 500 /
1CH
0
1
1
1
0
0 V28' V2+(V1-V2)× 400 /
1DH
0
1
1
1
0
1 V29' V2+(V1-V2)× 300 /
1EH
0
1
1
1
1
0 V30' V2+(V1-V2)× 200 /
1FH 0 1 1 1 1 1 V31' V2+(V1-V2)× 100 /
20H 1 0 0 0 0 0 V32' V2
21H 1 0 0 0 0 1 V33' V3+(V2-V3)× 1550 /
22H 1 0 0 0 1 0 V34' V3+(V2-V3)× 1450 /
23H 1 0 0 0 1 1 V35' V3+(V2-V3)× 1350 /
24H 1 0 0 1 0 0 V36' V3+(V2-V3)× 1250 /
25H 1 0 0 1 0 1 V37' V3+(V2-V3)× 1150 /
26H 1 0 0 1 1 0 V38' V3+(V2-V3)× 1050 /
27H 1 0 0 1 1 1 V39' V3+(V2-V3)× 950 /
28H 1 0 1 0 0 0 V40' V3+(V2-V3)× 850 /
29H 1 0 1 0 0 1 V41' V3+(V2-V3)× 750 /
2AH
1
0
1
0
1
0 V42' V3+(V2-V3)× 650 /
2BH
1
0
1
0
1
1 V43' V3+(V2-V3)× 550 /
2CH
1
0
1
1
0
0 V44' V3+(V2-V3)× 450 /
2DH
1
0
1
1
0
1 V45' V3+(V2-V3)× 350 /
V47' 2EH 1 0 1 1 1 0 V46' V3+(V2-V3)× 250 /
2FH 1 0 1 1 1 1 V47' V3+(V2-V3)× 150 /
V48' 30H 1 1 0 0 0 0 V48' V3
31H 1 1 0 0 0 1 V49' V4+(V3-V4)× 4100 /
V49' 32H 1 1 0 0 1 0 V50' V4+(V3-V4)× 3950 /
33H 1 1 0 0 1 1 V51' V4+(V3-V4)× 3800 /
34H 1 1 0 1 0 0 V52' V4+(V3-V4)× 3650 /
35H 1 1 0 1 0 1 V53' V4+(V3-V4)× 3500 /
36H 1 1 0 1 1 0 V54' V4+(V3-V4)× 3350 /
37H 1 1 0 1 1 1 V55' V4+(V3-V4)× 3200 /
38H 1 1 1 0 0 0 V56' V4+(V3-V4)× 2950 /
39H 1 1 1 0 0 1 V57' V4+(V3-V4)× 2700 /
3AH
1
1
1
0
1
0 V58' V4+(V3-V4)× 2450 /
V61' 3BH 1 1 1 0 1 1 V59' V4+(V3-V4)× 2150 /
3CH
1
1
1
1
0
0 V60' V4+(V3-V4)× 1850 /
V62' 3DH 1 1 1 1 0 1 V61' V4+(V3-V4)× 1550 /
3EH
1
1
1
1
1
0 V62' V4+(V3-V4)× 1100 /
3FH 1 1 1 1 1 1 V63' V4
V63'
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
7650
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
2300
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
1650
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
4250
rn
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r total
()
1150
700
700
700
700
350
350
350
350
350
350
350
350
300
300
300
200
200
200
200
200
150
150
150
150
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
150
150
150
150
150
150
150
150
250
250
250
300
300
300
450
1100
15850
Caution There is no connection between V4 and V5 terminal in the chip.
Data Sheet S14725EJ1V0DS00
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
UPD16772A

480-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64-GRAY SCALES

NEC
NEC
UPD16772AN

480-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64-GRAY SCALES

NEC
NEC

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