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W133 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 W133은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 W133 자료 제공

부품번호 W133 기능
기능 Spread Spectrum System Frequency Synthesizer
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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W133 데이터시트, 핀배열, 회로
PRELIMINARY
W133
Spread Spectrum System Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• Eight copies of PCI output (synchronous w/CPU output)
• Four copies of 66-MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
• Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
Key Specifications
Supply Voltages: ...................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
CPU Output Jitter: ...................................................... 250 ps
CPUdiv2 Output Jitter:.................................................250 ps
48 MHz, 3V66, PCI, IOAPIC Output Jitter: .................. 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew; ...........................250 ps
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-kpull-up
resistors.
Table 1. Pin Selectable Frequency[1]
SEL133/100#
CPU0:3 (MHz)
PCI
1
133 MHz
33.3 MHz
0
100 MHz
33.3 MHz
Note:
1. See Table 2 for complete mode selection details.
Pin Configuration
X1
X2
CPU_STOP#
SPREAD#
SEL0
SEL1
SEL133/100#
PWRDWN#
PCI_STOP#
XTAL
OSC
2
REF0:1
PLL 1
Power
Down
Logic
STOP
Clock
Logic
÷2
÷2/÷1.5
STOP
Clock
Logic
STOP
÷2 Clock
Logic
÷2
4
CPU0:3
2
CPUdiv2_0:1
4
3V66_0:3
1
PCI_F
7
PCI1:7
3
IOAPIC0:2
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDQ2
55 IOAPIC2
54 IOAPIC1
53 IOAPIC0
52 GND
51 VDDQ2
50 CPUdiv2_1
49 CPUdiv2_0
48 GND
47 VDDQ2
46 CPU3
45 CPU2
44 GND
43 VDDQ2
42 CPU1
41 CPU0
40 GND
39 VDDQ3
38 GND
37 PCI_STOP#
36 CPU_STOP#
35 PWRDWN#
34 SPREAD#
33 SEL1
32 SEL0
31 VDDQ3
30 48MHz
29 GND
Three-state
Logic
PLL2
1
48MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **




W133 pdf, 반도체, 판매, 대치품
PRELIMINARY
W133
Mode Selection Functions
The W133 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.
Table 2. Select Functions
SEL133/100#
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Function
All Outputs Three-State
(Reserved)
Active 100 MHz, 48 MHz PLL Inactive
Active 100 MHz, 48 MHz PLL Active
Test Mode
(Reserved)
Active 133 MHz, 48 MHz PLL Inactive
Active 133 MHz, 48 MHz PLL Active
Table 3. Truth Table
SEL
133/100#
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
HI-Z
n/a
100 MHz
100 MHz
TCLK/2
n/a
133 MHz
133 MHz
CPUdiv2
HI-Z
n/a
50 MHz
50 MHz
TCLK/4
n/a
66 MHz
66 MHz
3V66
HI-Z
n/a
66 MHz
66 MHz
TCLK/4
n/a
66 MHz
66 MHz
PCI
HI-Z
n/a
33 MHz
33 MHz
TCLK/8
n/a
33 MHz
33 MHz
48MHz
HI-Z
n/a
HI-Z
48 MHz
TCLK/2
n/a
HI-Z
48 MHz
REF
IOAPIC
HI-Z
HI-Z
n/a n/a
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
TCLK
TCLK16
n/a n/a
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
Notes
2
3
4, 7, 8
5, 6
3
4, 7, 8
Table 4. Maximum Supply Current
Condition
Powerdown Mode
(PWRDWN#=0)
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2=2.625V
All static inputs=VDDQ3 or GND
100 µA
Max. 3.3V supply consumption
Max. discrete cap loads,
VDDQ3=3.465V or GND
200 µA
FUll Active 100MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
75 mA
160 mA
Full Active 133MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
90 mA
Notes:
2. Provided for board level bed of nailstesting.
3. 48-MHz PLL disabled to reduce component jitter.
4. Normalmode of operation.
5. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
6. Required for DC output impedance verification.
7. Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz.
8. Frequency accuracy of 48 MHz is +167 PPM to match USB default.
160 mA
4

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W133 전자부품, 판매, 대치품
PRELIMINARY
W133
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
VDD, VIN
TSTG
TA
TB
ESDPROT
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Input ESD Protection
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
0.5 to +7.0
65 to +150
0 to +70
55 to +125
2 (min.)
Unit
V
°C
°C
°C
kV
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Supply Current
IDD-3.3V
Combined 3.3V Supply Current
IDD-2.5
Combined 2.5V Supply Current
Logic Inputs (All referenced to VDDQ3 = 3.3V)
VIL Input Low Voltage
CPU0:3 =133 MHz[29]
CPU0:3 =133 MHz[29]
GND
0.3
VIH Input High Voltage
IIL Input Low Current[30]
IIH Input High Current[30]
IIL Input Low Current, SEL133/100#[30]
IIH Input High Current, SEL133/100#[30]
Clock Outputs
2.0
CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2)
Test Condition
VOL Output Low Voltage
IOL = 1 mA
VOH Output High Voltage
IOH = 1 mA
IOL Output Low Current
VOL = 1.25V
IOH Output High Current
VOH = 1.25V
48MHz, REF (Referenced to VDDQ3)
Test Condition
VOL Output Low Voltage
IOL = 1 mA
VOH Output High Voltage
IOH = 1 mA
IOL Output Low Current
VOL = 1.5V
IOH Output High Current
VOH = 1.5V
PCI, 3V66 (Referenced to VDDQ3)
Test Condition
VOL Output Low Voltage
IOL = 1 mA
VOH Output High Voltage
IOH = 1 mA
IOL Output Low Current
VOL = 1.5V
IOH Output High Current
VOH = 1.5V
Notes:
29. All clock outputs loaded with 6" 60transmission lines with 20-pF capacitors.
30. W133 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
Min.
2.2
45
45
Min.
3.1
45
45
Min.
3.1
70
65
Typ.
65
65
Typ.
65
65
Typ.
100
95
Max.
Unit
160 mA
90 mA
0.8 V
VDD + 0.3
25
10
5
5
V
µA
µA
µA
µA
Max.
50
100
100
Max.
50
100
100
Max.
50
145
135
Unit
mV
V
mA
mA
Unit
mV
V
mA
mA
Unit
mV
V
mA
mA
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