W147G Datasheet PDF - Cypress Semiconductor
| Part Number | W147G | |
| Description | Frequency Generator for Integrated Core Logic | |
| Manufacturers | Cypress Semiconductor | |
| Logo |  |
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PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• Two copies of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
• Two copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power-down control
• I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps
CPU, 3V66 Output Skew: ............................................175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
SEL1
SEL0
00
01
10
11
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Block Diagram
X1
X2
SDATA
SCLK
SEL0:1
XTAL
OSC
PLL REF FREQ
I2C
Logic
D i vi d e r,
D el a y,
and
Phase
Control
Logic
PLL 1
PWRDWN#
VDDQ3
REF/APICDIV
VDDQ2
CPU0:1
2
CPU2_ITP
APIC0:1
2
VDDQ3
3V66_0:1
2
PCI0_ICH
PCI1:7
7
DCLK
SDRAM0:7
8
PLL2
VDDQ3
USB
DOT
Pin Configuration
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
USB
DOT
VDDQ3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 GND
55 APIC0
54 APIC1
53 VDDQ2
52 CPU0
51 VDDQ2
50 CPU1
49 CPU2_ITP
48 GND
47 GND
46 SDRAM0
45 SDRAM1
44 VDDQ3
43 SDRAM2
42 SDRAM3
41 GND
40 SDRAM4
39 SDRAM5
38 VDDQ3
37 SDRAM6
36 SDRAM7
35 GND
34 DCLK
33 VDDQ3
32 PWRDWN#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **
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PRELIMINARY
W147G
Power Down Control
W147G provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
25ns
1
50ns
2
Figure 4. W147G PWRDWN# Timing Diagram[8, 9, 10, 11]
75ns
Center
Table 3. W147G Maximum Allowed Current
W147
Condition
Powerdown Mode
(PWRDWN# = 0)
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2 = 2.625V
All static inputs = VDDQ3 or VSS
100 µA
Max. 3.3V supply consumption
Max. discrete cap loads
VDDQ3 = 3.465V
All static inputs = VDDQ3 or VSS
200 µA
Full Active 66 MHz
SEL1,0 = 10 (PWRDWN# =1)
70 mA
280 mA
Full Active 100 MHz
SEL1,0 =11 (PWRDWN# = 1)
100 mA
280 mA
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
transition.
9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
5
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| Information | Total 12 Pages | |
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Featured Datasheets
| Part Number | Description | MFRS |
| W147 | The function is Frequency Generator for Integrated Core Logic. Cypress Semiconductor | |
| W147G | The function is Frequency Generator for Integrated Core Logic. Cypress Semiconductor | |
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