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부품번호 | W167B 기능 |
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기능 | 133-MHz Spread Spectrum FTG for Pentium II Platforms | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
전체 18 페이지수
PRELIMINARY
W167B
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU outputs selectable frequency
• Three copies of 3V66 selectable frequency output at
3.3V
• Ten copies of PCI clocks (selectable frequency), 3.3V
• One double strength 14.318-MHz reference output at
3.3V
• One copy of 48-MHz USB clock
• One copy of selectable 24-/48-MHz for SIO
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Three copies of IOAPIC
• Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... VDDQ2 = 2.5V±5%
VDDQ3 = 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Block Diagram
X1 XTAL
X2 OSC
VDDQ3
REF2X
VDDQ2
CPU_[0:2]
3
SEL133/100#
PLL 1
÷2
÷2/÷1.5
PWRDWN#
Power
Down
Logic
÷2
÷2
SDATA
SCLK
PLL2
Serial
Logic
÷2
CPUdiv2
VDDQ3
3V66_[0:2]
3
PCI0/SEL2*
PCI1/SEL1*
PCI_[2:9]
8
VDDQ2
IOAPIC[0:2]
3
QVD# DQ3
48MHz/SEL0*
SIO/24_48#MHz
Duty Cycle: ................................................................ 45/55%
Spread Spectrum Modulation:................................... ±0.25%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/
CPU 3V66 PCI IOAPIC
100# SEL2 SEL1 SEL0 MHz MHz MHz MHz
1 1 1 1 133.3 66.7 33.3 16.7
1 1 1 0 138 69 34.5 17.3
1 1 0 1 143 71.5 35.8 17.9
1 1 0 0 148 74 37 18.5
1 0 1 1 150 75 37.5 18.8
1 0 1 0 152.5 76.3 38.1 19.1
1 0 0 1 155 77.5 38.8 19.4
1 0 0 0 160 80 40 20
0 1 1 1 100.2 66.8 33.4 16.7
0 1 1 0 105 70 35 17.5
0 1 0 1 114 76 38 19
0 1 0 0 120 80 40 20
0 0 1 1 66.8 66.8 33.4 16.7
0 0 1 0 124 82.7 41.3 20.7
0 0 0 1 128.5 64.3 32.1 16.1
0 0 0 0 133.9 67 33.5 16.7
Pin Configuration[1]
IOAPIC2
REF2X
VDDQ3
X1
X2
GND
SEL2*/PCI0
SEL1*/PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 VDDQ2
46 IOAPIC0
45 IOAPIC1
44 GND
43 VDDQ2
42 CPUdiv2
41 GND
40 VDDQ2
39 CPU2
38 GND
37 VDDQ2
36 CPU1
35 CPU0
34 SDATA
33 VDDQ3
32 GND
31 PWRDN#*
30 SCLK
29 VDDQ3
28 SIO/24_48#MHz*
27 48MHz/SEL0*
26 GND
25 SEL133/100#
Note:
1. Internal 250-kΩ pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999
PRELIMINARY
W167B
CPU/PCI Frequency Selection
CPU frequency is selected with I/O pins 7, 8, 27, (SEL2/PCI0,
SEL1/PCI1, 48MHz/SEL0, respectively) and input pin 25
(SEL133/100#). Refer to Table 1 for CPU/PCI frequency pro-
gramming information. Additional frequency selections are
available through the serial data interface. Refer to Table 5 on
page 9.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The W167B outputs are CMOS-type which provide rail-
to-rail output swing.
Crystal Oscillator
The W167B requires one input reference clock to synthesize
all output frequencies. The reference clock can be either an
externally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W167B incor-
porates the necessary feedback resistor and crystal load ca-
pacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 18 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
18 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm.
4
4페이지 PRELIMINARY
W167B
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–6. Table 5 details additional frequency selections that
are available through the serial data interface. Table 6 details
the select functions for Byte 0, bits 1 and 0.
Table 4. Data Bytes 0–6 Serial Configuration Map
Affected Pin
Bit(s) Pin No. Pin Name
Control Function
Data Byte 0
7 --
-- SEL133/100#
6 --
-- SEL2
5 --
-- SEL1
4 --
-- SEL0
3 --
-- Frequency Table Selection
2 --
1-0
--
Data Byte 1
7 27
6 28
5 --
4 42
3 --
2 39
1 36
0 35
Data Byte 2
7 16
6 15
5 13
4 12
3 11
2 10
18
07
Data Byte 3
7 --
6 23
5 22
4 21
3 --
2 --
1 19
0 18
-- (Reserved)
-- Functional control
48MHz
24/48MHz
--
CPUdiv2
--
CPU2
CPU1
CPU0
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
3V66_2
3V66_1
3V66_0
--
--
PCI9
PCI8
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Bit Control
01
Default
Refer to Table 5
Refer to Table 5
Refer to Table 5
Refer to Table 5
Controlled by exter- Controlled by BYTE0
nal pin (per Table 1)
(per Table 5)
-- --
Refer to Table 6
0
0
0
0
0
0
00
Low
Active
1
Low
Active
1
-- -- 0
Low
Active
1
-- -- 0
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
-- -- 0
Low
Active
1
Low
Active
1
Low
Active
1
-- -- 0
-- -- 0
Low
Active
1
Low
Active
1
7
7페이지 | |||
구 성 | 총 18 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
W167B | 133-MHz Spread Spectrum FTG for Pentium II Platforms | Cypress Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |