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부품번호 | W182 기능 |
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기능 | Full Feature Peak Reducing EMI Solution | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
전체 8 페이지수
W182
Full Feature Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz ≤ Fin ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
SS%
0
1
W182
Output
Fin ≥ Fout ≥ Fin
– 1.25%
Fin ≥ Fout ≥ Fin
– 3.75%
W182-5
Output
Fin + 0.625% ≥ Fin≥
– 0.625%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2 FS1
00
01
10
11
Frequency Range
8 MHz ≤ FIN ≤ 10 MHz
10 MHz ≤ FIN ≤ 15 MHz
15 MHz ≤ FIN ≤ 18 MHz
18 MHz ≤ FIN ≤ 28 MHz
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
XTAL
Input
X1
X2
W182
Spread Spectrum
Output
(EMI suppressed)
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
1
2
3
4
5
6
7
14 REFOUT
13 OE#
12 SSON#
11 Reset
10 VDD
9 VDD
8 CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W182
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 8, 2000, rev. *A
W182
Spread Spectrum Frequency Timing
Generation
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
SSFTG
Typical Clock
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Center Spread
Frequency Span (MHz)
Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
4
4페이지 W182
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended a 2-layer board layout.
Xtal Connection or Reference Input 1
14
Xtal Connection or NC
GND
2
3
4
13
12
11
5 10
69
78
R1
Clock
Output
3.3V or 5V System Supply
FB
C1
0.1 µF
C3
0.1µF
C2
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
Xtal Connection or Reference Input
Xtal Connectionor NC
G
G
C1, C3 = High-frequency supply decoupling
capacitor (0.1-µF recommended).
C2 = Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
R1 = Match value to line impedance
FB = Ferrite Bead
G = Via To GND Plane
C3
G
C1
G
Power Supply Input
(3.3V or 5V)
R1
G
FB C2
Clock Output
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
Package
Name
W182
W182-5
G
Package Type
14-Pin Plastic SOIC (150-mil)
Document #: 38-00789-A
7
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부품번호 | 상세설명 및 기능 | 제조사 |
W180 | Peak Reducing EMI Solution | Cypress Semiconductor |
W181 | Peak Reducing EMI Solution | Cypress Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |