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PDF W182-5 Data sheet ( Hoja de datos )
| Número de pieza | W182-5 | |
| Descripción | Full Feature Peak Reducing EMI Solution | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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W182
Full Feature Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz ≤ Fin ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
SS%
0
1
W182
Output
Fin ≥ Fout ≥ Fin
– 1.25%
Fin ≥ Fout ≥ Fin
– 3.75%
W182-5
Output
Fin + 0.625% ≥ Fin≥
– 0.625%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2 FS1
00
01
10
11
Frequency Range
8 MHz ≤ FIN ≤ 10 MHz
10 MHz ≤ FIN ≤ 15 MHz
15 MHz ≤ FIN ≤ 18 MHz
18 MHz ≤ FIN ≤ 28 MHz
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
XTAL
Input
X1
X2
W182
Spread Spectrum
Output
(EMI suppressed)
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
1
2
3
4
5
6
7
14 REFOUT
13 OE#
12 SSON#
11 Reset
10 VDD
9 VDD
8 CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W182
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 8, 2000, rev. *A
1 page  
W182
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
VDD, VIN
TSTG
TA
TB
PD
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
IDD Supply Current
tON Power Up Time
First locked clock cycle after Power
Good
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
IIL
Input Low Current
Note 1
IIH
Input High Current
Note 1
IOL
Output Low Current
@ 0.4V, VDD = 3.3V
IOH
Output High Current
@ 2.4V, VDD = 3.3V
CI Input Capacitance
RP Input Pull-Up Resistor
ZOUT
Clock Output Impedance
Note:
1. Inputs FS2:1 have a pull-up resistor; Input SSON# has a pull-down resistor.
Min.
2.4
2.4
–50
Typ.
18
15
15
500
25
Max.
32
5
0.8
0.4
50
7
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
kΩ
Ω
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet W182-5.PDF ] | |
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